Commit graph

82384 commits

Author SHA1 Message Date
Jason Ekstrand
5d9afb65a6 i965/peephole_ffma: Only match a mul+add if none of the ops are exact 2016-03-28 13:07:39 -07:00
Jason Ekstrand
035f66025b nir/search: Don't match inexact expressions with exact subexpressions
In the first pass of implementing exact handling, I made a mistake with
search-and-replace.  In particular, we only reallly handled exact/inexact
on the root of the tree.  Instead, we need to check every node in the tree
for an exact/inexact match.  As an example of this, consider the following
GLSL code

precise float a = b + c;
if (a < 0) {
   do_stuff();
}

In that case, only the add will be declared "exact" and an expression that
looks for "b + c < 0" will still match and replace it with "b < -c" which
may yield different results.  The solution is to simply bail if any of the
values are exact when matching an inexact expression.
2016-03-28 13:07:39 -07:00
Rhys Kidd
668b6ddfc5 vc4: Remove unused include from vc4_nir_lower_txf_ms.c
Found with grep and inspection. Test compiled on RPi hw.
Assists any future effort to remove TGSI as an intermediate stage.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2016-03-28 11:51:11 -07:00
Adam Jackson
2b8492d63e glapi/glx: Treat xserver generated targets as .PHONY
Meaning, always rebuild them when asked instead of bothering to look at
timestamps (and then wondering why nothing happened when you said make).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2016-03-28 14:37:12 -04:00
Adam Jackson
c2f0bc2537 glapi/glx: Thunk non-ABI calls through GetProcAddress
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2016-03-28 14:37:12 -04:00
Adam Jackson
ce3f0b23d1 glapi/glx: Emit direct GL calls instead of dispatch lookup
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2016-03-28 14:28:51 -04:00
Adam Jackson
c0a9cbea4d glx: Unbreak generating some of the xorg glx headers
Broken by:

    commit 9ace0b5422
    Author: Dylan Baker <baker.dylan.c@gmail.com>
    Date:   Wed May 20 15:49:11 2015 -0700

	glapi: glX_proto_size.py: use argparse instead of getopt

Which changed most, but not all, callers to use --header-tag instead of
-h.

Reviewed-by: Dylan Baker <baker.dylan.c@gmail.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2016-03-28 14:28:36 -04:00
Bas Nieuwenhuizen
dd5f0950e4 mesa/st: Fix NULL access if no fragment shader is bound
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-28 18:02:07 +02:00
Rob Clark
b4c72b792c freedreno/ir3: fix for load_front_face intrinsic
Seems like trying to widen in the same instruction as the add.s does a
non-sign-extending widen.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-03-28 10:19:53 -04:00
Rob Clark
3ca034cada freedreno/ir3: fix compiler warn
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-03-28 10:19:09 -04:00
Ilia Mirkin
b9f1affb2e nvc0: make sure to disable fetches from previously-set VBOs when blitting
We disable the vertex attributes, but also disable the VBO fetch details
as well, just in case. Not known to fix anything.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-28 08:36:34 -04:00
Ilia Mirkin
41100b6b44 nvc0: disable primitive restart and index bias during blits
Back in the dawn of time, we used to do immediate uploads for the vertex
data, and all was well. However Maxwell dropped support for immediate
vertex data, so we started feeding in a VBO (in all cases). But we
forgot to disable some things that apply in such cases, specifically
primitive restart and index bias. The latter was causing WoW and other
Blizzard games trouble as they use a pattern where they draw with a base
vertex (aka index bias), followed by texture uploads (aka blits,
internally).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Karol Herbst <nouveau@karolherbst.de>
2016-03-28 08:35:38 -04:00
Ilia Mirkin
f667d15561 nvc0/ir: fix picking of coordinates from tex instruction for textureGrad
On Fermi, there's an argument in front of the coords that combines array
and indirect handle, while on Kepler the array and the indirect handle
are separate (and in front of the coords). We were previously only
accounting for the array bit of it, if there were an indirect access it
wouldn't be counted in the formula.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-28 08:35:38 -04:00
Ilia Mirkin
6711f159d9 nv50/ir: saturate depth writes
Apparently there's no post-FS clamping logic, so we have to do this by
hand. The depth will never be outside of the 0..1 range, even on
floating point zeta buffers, so this should be safe.

Fixes dEQP-GLES3.functional.fbo.depth.*clamp.* which tests writing
invalid values on various zeta buffer formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-28 08:35:38 -04:00
Marek Olšák
6262d6125a gallium/util: fix up inaccurate behavior of util_framebuffer_state_equal (v2)
v2: move the nr_cbufs check above the loop

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
2016-03-28 00:46:23 +02:00
Marek Olšák
21c479256a st/mesa: only minify height if target != 1D array in st_finalize_texture
The st_texture_object documentation says:
  "the number of 1D array layers will be in height0"

We can't minify that.

Spotted by luck. No app is known to hit this issue.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-28 00:44:45 +02:00
Miklós Máté
50d653c2bb mesa: optimize out the realloc from glCopyTexImagexD()
v2: comment about the purpose of the code
v3: also compare texFormat,
 add a perf debug message,
 formatting fixes

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 19:58:33 +02:00
Miklós Máté
baab345b19 st/mesa: fix handling the fallback texture
This fixes crash when post-processing is enabled in SW:KotOR.

v2: fix const-ness
v3: move assignment into the if() block

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 19:58:33 +02:00
Miklós Máté
920fbecf57 st/mesa: enable GL_ATI_fragment_shader
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 19:58:33 +02:00
Miklós Máté
dee274477f st/mesa: implement GL_ATI_fragment_shader
v2: fix arithmetic for special opcodes,
 fix fog state, cleanup
v3: simplify handling of special opcodes,
 fix rebinding with different textargets or fog equation,
 lots of formatting fixes
v4: adapt to the compile early, fix later architecture,
 formatting fixes

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 19:58:33 +02:00
Miklós Máté
d71c1e9e54 program: add ATI_fragment_shader to shader stages list
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 19:58:33 +02:00
Miklós Máté
e2d5a6fac5 mesa: optionally associate a gl_program to ATI_fragment_shader
the state tracker will use it

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 19:58:33 +02:00
Edward O'Callaghan
11bd53933e gallium/p_context.h: Make comment more readable
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 18:03:04 +02:00
Edward O'Callaghan
2df141087a mesa/st: Remove GLSLVersion clamping
While here, remove itermediate glsl_feature_level variable.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 18:00:36 +02:00
Edward O'Callaghan
ca22d2f1fd radeon/r600: Fix return type in failure branch
Commit `d4e847ea` introduced a warning about making an
integer from a pointer without a cast, fix it here.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 18:00:35 +02:00
Edward O'Callaghan
1fb05a9a0c radeon/r600_query.c: Minor style fix
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-03-27 18:00:35 +02:00
Dave Airlie
fc3b000fef virgl: drop next shader property for now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-03-26 17:50:32 +10:00
Jason Ekstrand
6d658e9bd5 i965: Allow mul+add fusing again 2016-03-25 21:35:41 -07:00
Jason Ekstrand
fbb9e1f008 spirv/alu: Add support for the NoContraction decoration 2016-03-25 21:35:41 -07:00
Jason Ekstrand
00fa795cd3 spirv/glsl: Add a helper for converting glsl opcodes into nir opcodes
This is similar to the way that regular ALU operations are handled.
2016-03-25 21:35:41 -07:00
Jason Ekstrand
98522c1853 nir/spirv: Get rid of the spirv2nir helper binary
This was useful once upon a time but now that we have a real Vulkan driver
to run our SPIR-V binaries through, there's really no point.
2016-03-25 21:35:41 -07:00
Nanley Chery
0e82896a11 anv/blit2d: Add a function to create an ImageView
This function differs from the open-coded implementation in that the
ImageView's width is determined by the caller and is not unconditionally
set to match the number of texels within the surface's pitch.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-25 17:33:50 -07:00
Nanley Chery
4eab37d6cd anv/image: Enable specifying a surface's minimum pitch
This is required to create multiple, horizontally adjacent, max-width
images from one blit2d surface. This is also required for more accurate
width specification of surfaces within a larger surface (which is seen
as the smaller surface's enclosing region).

Note that anv_image_create_info::stride has been unused since commit,
b369389640 .

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-25 17:33:40 -07:00
Timothy Arceri
8683d54d2b glsl: reduce buffer block duplication
This reduces some of the craziness required for handling buffer
blocks. The problem is each shader stage holds its own information
about a block in memory, we were copying that information to a
program wide list but the per stage information remained meaning
when a binding was updated we needed to update all versions of it.

This changes the per stage blocks to instead point to a single
version of the block information in the program list.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2016-03-26 09:26:30 +11:00
Jason Ekstrand
38250a9ca3 i965/vec4: Get rid of a stray predicate inverse in opquantizef16
This fixes 30 opquantize CTS tests on HSW
2016-03-25 14:37:37 -07:00
Jason Ekstrand
13bad493b4 nir/algebraic: Get rid of a redundant copy of fdiv lowering 2016-03-25 14:04:05 -07:00
Jason Ekstrand
08fe89864b nir/algebraic: Add better lowering of ldexp 2016-03-25 14:04:05 -07:00
Jason Ekstrand
b75d770963 nir/builder: Simplify nir_ssa_undef a bit 2016-03-25 14:04:05 -07:00
Jason Ekstrand
ab31951bef nir/spirv: Use the nir_ssa_undef helper from nir_builder 2016-03-25 14:04:05 -07:00
Jason Ekstrand
d2eee52a65 nir/builder: Add a bit size field to nir_ssa_undef 2016-03-25 14:04:05 -07:00
Jason Ekstrand
b50f7f0011 nir: Add a better comment for INTRINSIC_RANGE 2016-03-25 14:04:05 -07:00
Jason Ekstrand
add8c837b5 nir/glsl: Stop carying a pointer to the nir_shader in the visitor 2016-03-25 14:04:05 -07:00
Brian Paul
a8e5edaadf st/xa: emit sampler view declarations in shaders
Fixes recent regressions with the VMware gallium driver.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Charmaine Lee <charmainel@vmware.com>
2016-03-25 14:53:59 -06:00
Tim Rowley
74a04840e5 swr: [rasterizer jitter] Fix MASKLOADD AVX prototype (float -> i32) 2016-03-25 14:45:40 -05:00
Tim Rowley
93c1a2dedf swr: [rasterizer core] NUMA optimizations...
- Affinitize hot-tile memory to specific NUMA nodes.
- Only do BE work for macrotiles assoicated with the numa node
2016-03-25 14:45:40 -05:00
Tim Rowley
090be2e434 swr: [rasterizer jitter] Fix logic bug for alpha-to-coverage. 2016-03-25 14:45:40 -05:00
Tim Rowley
0767e820fd swr: [rasterizer core] Fix Compute workitem retirement 2016-03-25 14:45:40 -05:00
Tim Rowley
813e89c0cc swr: [rasterizer core] Cleanup state ring arena after last draw that references it completes
Rather than waiting for the API thread to re-use it.
2016-03-25 14:45:40 -05:00
Tim Rowley
83822d7ed5 swr: [rasterizer jitter] add missing include for llvm jitevents 2016-03-25 14:45:40 -05:00
Tim Rowley
51549912d1 swr: [rasterizer core] Reduce Arena blocksize to 128KB (from 1MB).
With global allocator this doesn't seem to affect performance at all.
Overall memory consumption drops by up to 85%.
2016-03-25 14:45:40 -05:00