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Author SHA1 Message Date
Tim Rowley
ed5b953919 swr: [rasterizer core] One last pass at Arena optimizations 2016-03-25 14:45:40 -05:00
Tim Rowley
ee6be9e92d swr: [rasterizer core] CachedArena optimizations 
Reduce list traversal during Alloc and Free.

Add ability to have multiple lists based on alloc size (not used for now)
 2016-03-25 14:45:39 -05:00
Tim Rowley
68314b6769 swr: [rasterizer jitter] support llvm-svn 2016-03-25 14:45:39 -05:00
Tim Rowley
ec9d4c4b37 swr: [rasterizer core] Globally cache allocated arena blocks for fast re-allocation. 2016-03-25 14:45:39 -05:00
Tim Rowley
12ce9d9aa1 swr: [rasterizer] more arena work 2016-03-25 14:45:39 -05:00
Tim Rowley
4893224e28 swr: [rasterizer core] Add clipping against user clip distances in the NullPS backend. 2016-03-25 14:45:39 -05:00
Tim Rowley
700a5b06e0 swr: [rasterizer core] Arena optimizations - preparing for global allocator. 2016-03-25 14:45:39 -05:00
Tim Rowley
5899076b6b swr: [rasterizer core] Reset DrawContext arena at end of draw rather than upon reclaim of DC 
Keeps overall memory consumption lower.
Also, remove unused knobs.
 2016-03-25 14:45:39 -05:00
Tim Rowley
7390418441 swr: [rasterizer core] Add clipping of user clip planes in clipper. 2016-03-25 14:45:39 -05:00
Tim Rowley
4b4547a721 swr: [rasterizer] Reduce max in-flight draws to 96 (by default) 2016-03-25 14:45:39 -05:00
Tim Rowley
9111d63228 swr: [rasterizer] Fix run-time check asserts 
One innocuous (uninitialized variable), and one not so innocuous
(stack corruption).
 2016-03-25 14:45:39 -05:00
Tim Rowley
257db3610a swr: [rasterizer jitter] signed immediate builder 2016-03-25 14:45:39 -05:00
Tim Rowley
b958aea78a swr: [rasterizer common] changes for cygwin 2016-03-25 14:45:39 -05:00
Tim Rowley
e1222ade00 swr: [rasterizer] code styling and update copyrights 2016-03-25 14:45:14 -05:00
Tim Rowley
c75314ec67 swr: [rasterizer core] Guard against enquing work to invalid hot tiles 2016-03-25 14:43:15 -05:00
Tim Rowley
fee56fda6f swr: [rasterizer] Stop setting viewport size to larger than hottile array 
Guard against enquing work to invalid tiles
 2016-03-25 14:43:14 -05:00
Tim Rowley
e374d2d24b swr: [rasterizer] Discard work + misc fixes 2016-03-25 14:43:14 -05:00
Tim Rowley
542d7dec7b swr: [rasterizer] remove use of BYTE type 2016-03-25 14:43:14 -05:00
Tim Rowley
be4c558d01 swr: [rasterizer core] Fix crash that can occur when switching contexts 2016-03-25 14:43:14 -05:00
Tim Rowley
51a11658d9 swr: [rasterizer] remove unused knob 2016-03-25 14:43:14 -05:00
Tim Rowley
61beaa2279 swr: [rasterizer core] subcontext rework 2016-03-25 14:43:14 -05:00
Tim Rowley
0c18900cfb swr: [rasterizer common] add _simd_s[rl]lv_epi32 2016-03-25 14:43:14 -05:00
Tim Rowley
bef222db22 swr: [rasterizer core] Alleviate potential stack overflow for 32bit builds 
Move large stack allocations in the GS and clipper into thread local storage.
 2016-03-25 14:43:14 -05:00
Tim Rowley
3132f731f8 swr: [rasterizer] remove use of UCHAR and UINT64 types 2016-03-25 14:43:14 -05:00
Tim Rowley
643857f596 swr: [rasterizer] remove use of FLOAT type 2016-03-25 14:43:14 -05:00
Tim Rowley
3252fe3705 swr: [rasterizer] Fix Coverity issues reported by Mesa developers. 2016-03-25 14:43:14 -05:00
Tim Rowley
45d52673c2 swr: [rasterizer] add debug/perf category to knobs 2016-03-25 14:43:13 -05:00
Tim Rowley
1da9c8a970 swr: [rasterizer core] don't assume linux is 64-bit 2016-03-25 14:43:13 -05:00
Tim Rowley
49678803f7 swr: [rasterizer common] remove old unused win32 types 2016-03-25 14:43:13 -05:00
Tim Rowley
aca5513184 swr: [rasterizer jitter] vpermps support 2016-03-25 14:43:13 -05:00
Tim Rowley
bfb954189e swr: [rasterizer] Add rdtsc buckets support for shaders 
Pass pointer to core buckets mgr back to sim layer.

Add support for RDTSC_START/RDTSC_STOP macros in the builder.

Each unique shader now has a unique bucket associated with it,
enabling more detailed reporting at the shader level. Currently
due to some llvm issue with thread local storage, 64bit runs require
single threaded mode.
 2016-03-25 14:43:13 -05:00
Tim Rowley
abd4aa68cc swr: [rasterizer core] backend reorganization 2016-03-25 14:43:13 -05:00
Tim Rowley
13303f3320 swr: [rasterizer core] store blend output in temporary instead of PS output. 
Fixes additive blend problem with MSAA
 2016-03-25 14:26:17 -05:00
Tim Rowley
3f4fba3772 swr: [rasterizer core] Move InitializeHotTiles and corresponding clear code out of threads.cpp. 2016-03-25 14:26:17 -05:00
Tim Rowley
bdd690dc36 swr: [rasterizer jitter] Cleanup use of types inside of Builder. 
Also, cached the simd width since we don't have to keep querying
the JitManager for it.
 2016-03-25 14:26:17 -05:00
Tim Rowley
7ead4959a5 swr: [rasterizer jitter] Fix type mismatch on select args for SCATTERPS 2016-03-25 14:26:17 -05:00
Tim Rowley
136988b42b swr: [rasterizer core] fix rasterizing multisampling with scissor enabled 
We were not evaluating the scissor edge equations at sample positions.
 2016-03-25 14:26:17 -05:00
Tim Rowley
45f0ce168c swr: [rasterizer core] RingBuffer class for DC/DS 
Use head/tail ring buffer indices for thread synchronization.

1. SwrWaitForIdle loops until ring is empty. (head == tail)
2. GetDrawContext waits until ring is not full. (head - tail) == Ring Size
3. Draw enqueues by incrementing head.
4. Last worker thread to move past a DC dequeues by incrementing tail.

Todo: To reduce contention we can cache the tail in the API thread. For
example, if you know you have 64 free entries in the ring then you don't
need to keep checking the tail until you used those 64 entries.
 2016-03-25 14:26:17 -05:00
Tim Rowley
dd0f9eed8c swr: [rasterizer] switch assert uses to SWR_ASSERT 2016-03-25 14:26:16 -05:00
Tim Rowley
45a4afa634 swr: [rasterizer core] Split all RECT_LIST draws into 1 RECT per draw 
Needed until proper RECT_LIST PrimAssembly code is written.
 2016-03-25 14:26:16 -05:00
Tim Rowley
3a25185990 swr: [rasterizer] Add string knob type 2016-03-25 14:26:16 -05:00
Jordan Justen
8f3c236674 anv: Use genxml register support for L3 Cache config 
The programming of the L3 Cache registers should match the previous
manually packed LRI values.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2016-03-25 00:19:18 -07:00
Jordan Justen
7a03fb9ccb genxml: Add L3 Cache Control register definitions 
Based on intel_reg.h (5912da45a6)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2016-03-24 23:49:53 -07:00
Jordan Justen
d353ba8f5f anv: Add genxml register support 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2016-03-24 23:49:53 -07:00
Jordan Justen
b332013a56 genxml: Add register support 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2016-03-24 23:46:59 -07:00
Sonny Jiang
f00c840578 radeonsi: add Polaris PCI IDs 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (Polaris10)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (Polaris11)
 2016-03-24 23:08:12 -04:00
Sonny Jiang
f87ed903fb radeon/vce: disable two pipe mode for Polaris11 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
 2016-03-24 23:08:04 -04:00
Sonny Jiang
0c5477465f radeon/vce: add Polaris11 VCE firmware support 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
 2016-03-24 23:07:53 -04:00
Sonny Jiang
42e442d888 radeonsi: add support for Polaris (v2) 
v2: Polaris chips should be defined after Stoney

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> (v1)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Signed-off-by: Leo Liu <leo.liu@amd.com> (v2 diff)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2 diff)
 2016-03-24 23:07:32 -04:00
Sonny Jiang
f5e24b19e8 winsys/amdgpu: addrlib - add Polaris support (v2) 
v2: fix indentation as noted by Michel

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2016-03-24 23:06:39 -04:00