Commit graph

82384 commits

Author SHA1 Message Date
Eric Anholt
7030eadbed vc4: Handle nir_intrinsic_load_user_clip_plane as a vec4.
I liked having all my NIR be scalar, but nir_validate() complains that the
intrinsic writes 4 components but the destination we set up was only 1
component.  I could generate a new scalar variant, but it's a lot easier
to just leave it as a vec4.  This doesn't hurt codegen since we GC unused
uniforms, and UCP dot products use all the components anyway.
2016-04-08 18:40:55 -07:00
Rhys Kidd
40e77741cf vc4: Emit a warning and proceed for handling loops in NIR.
We don't really suppor control flow yet, but it's a lot nicer to render
something and warn on stderr than to crash.

Fixes the following piglit tests:
- shaders/complex-loop-analysis-bug
- shaders/glsl-fs-discard-04

Converts the following piglit tests from crash to fail:
- shaders/glsl-fs-continue-inside-do-while
- shaders/glsl-fs-loop
- shaders/glsl-fs-loop-continue
- shaders/glsl-fs-loop-nested
- shaders/glsl-texcoord-array
- shaders/glsl-vs-continue-inside-do-while
- shaders/glsl-vs-loop
- shaders/glsl-vs-loop-continue
- shaders/glsl-vs-loop-nested

No piglit regressions.

v2 (Eric): Add stronger stderr warning.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-04-08 18:28:43 -07:00
Rhys Kidd
2450b219e5 vc4: Add a stub for NIR->QIR of control flow function nodes
We shouldn't have any NIR functions present since all GLSL functions get
inlined, but this would be a more informative error if it does happen.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-04-08 18:28:43 -07:00
Rhys Kidd
e5997778bc vc4: Add better debug of NIR->QIR control flow graph failure
Ensure NIR control flow graph nodes that are unhandled in QIR
are reported with sufficient verbosity to aid debugging.

This improves piglit outputs, amongst other tools.

There are no other remaining uses of assert(0) as a blunt tool
within vc4.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-04-08 18:28:43 -07:00
Rhys Kidd
e529dd179f vc4: Remove unused include from vc4_program.c
Found with grep and inspection. Test compiled on RPi hw.
Assists any future effort to remove TGSI as an intermediate stage.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-04-08 18:28:43 -07:00
Lars Hamre
e25c24c638 glsl: handle unsigned int wraparound in link_shaders()
v2: change check_explicit_uniform_locations() to return an
    unsigned 0 (Timothy Arceri)

We were storing the int result of check_explicit_uniform_locations()
in num_explicit_uniform_locs as an unsigned int which caused it to
be 4294967295 when a -1 was returned.

This in turn would cause the following error during linking:
error: count of uniform locations > MAX_UNIFORM_LOCATIONS(4294967295 > 98304)

Results from running piglit tests/all with this patch
and when ARB_explicit_uniform_location disabled:

changes:     178
fixes:       176
regressions: 2

The two regressions are for the following tests:
glean@glsl1-matrix column check (1)
glean@glsl1-matrix column check (2)
which regress from FAIL to CRASH.

The regressions are acceptable because the tests are currently failing due to
the aforementioned linker error.

Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-04-09 11:06:04 +10:00
Jason Ekstrand
d4a28ae52a anv/meta: Make clflushes conditional on !devinfo->has_llc 2016-04-08 17:07:49 -07:00
Jason Ekstrand
c226e72a39 anv/formats: Advertise blit support for stencil
Thanks to advances in the blit code, we can do this now.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:59:29 -07:00
Jason Ekstrand
e3312644cb anv/blit2d: Add support for W-tiled destinations
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-04-08 15:59:26 -07:00
Jason Ekstrand
0a6842c1bd isl/surface_state: Set the correct pitch for W-tiled surfaces
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:52 -07:00
Jason Ekstrand
2e827816fa anv/blit2d: Add another passthrough varying to the VS
We need the VS to provide some setup data for other stages.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:49 -07:00
Jason Ekstrand
b377c1d08e anv/image: Remove the offset parameter from image_view_init
The only place we were using this was in meta_blit2d which always creates a
new image anyway so we can just use the image offset.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:45 -07:00
Jason Ekstrand
f9a2570a06 anv/blit2d: Add a bind_dst helper function
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:42 -07:00
Jason Ekstrand
15a9468d85 anv/blit2d: Simplify create_iview
Now it just creates the image and view.  The caller is responsible for
handling the offset calculations.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:40 -07:00
Jason Ekstrand
b8f3909b73 nir/gather_info: Handle discard_if
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:36 -07:00
Jason Ekstrand
819d0e1a7c anv/meta2d: Add support for blitting from W-tiled sources on gen7
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-04-08 15:58:03 -07:00
Jason Ekstrand
b0a5ca5cfc isl: Remove surf_get_intratile_offset_el
The intratile offset may not be a multiple of the element size so this
calculation is invalid.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:58:01 -07:00
Jason Ekstrand
b37502b983 isl: Rework the get_intratile_offset function
The old function tried to work in elements which isn't, strictly speaking,
a valid thing to do.  In the case of a non-power-of-two format, there is no
guarantee that the x offset into the tile is a multiple of the format
block size.  This commit refactors it to work entirely in terms of a tiling
(not a surface) and bytes/rows.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:58 -07:00
Jason Ekstrand
4caba94086 anv/image: Expose the guts of CreateBufferView for meta
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:55 -07:00
Jason Ekstrand
4ee80e8816 anv/blit2d: Refactor in preparation for different src/dst types
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:52 -07:00
Jason Ekstrand
85b9a007ac anv/blit2d: Add layouts for using a texel buffer source
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:49 -07:00
Jason Ekstrand
28eb02e345 anv/blit2d: Rename the descriptor set and pipeline layouts
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:47 -07:00
Jason Ekstrand
00e70868ee anv/blit2d: Enhance teardown and clean up init error paths
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:45 -07:00
Jason Ekstrand
43fbdd7156 anv/blit2d: Factor binding the source image into a helper
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:43 -07:00
Jason Ekstrand
5187ab05b8 anv/blit2d: Inline meta_emit_blit2d
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:41 -07:00
Jason Ekstrand
b0a6cfb9b4 anv/blit2d: Pass the source pitch into the shader
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:39 -07:00
Jason Ekstrand
e466164c87 anv/blit2d: Break the texelfetch portion of shader building into a helper
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:37 -07:00
Jason Ekstrand
afada45590 anv/blit2d: Fix whitespace
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:35 -07:00
Jason Ekstrand
9553fd2c97 anv/blit2d: Fix a NIR writemask
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:32 -07:00
Jason Ekstrand
b38a0d64ba anv/meta2d: Don't declare an array sampler in the fragment shader
With the new blit framework we aren't using array textures and, from
talking with Nanley, we don't think it's going to be useful in the future
either.  Just get rid of it for now.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:57:28 -07:00
Jason Ekstrand
dd6f720046 anv/blit2d: Remove the tex_dim parameter from copy_fragment_shader
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-04-08 15:56:52 -07:00
Jason Ekstrand
6cc7aec5b0 i965/tiled_memcopy: Get rid of the direction parameter to get_memcpy
Now that we can use the much simpler rgba8_copy function, we don't need to
hand different functions out based on direction.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-04-08 12:09:20 -07:00
Jason Ekstrand
d2b32656e1 i965/tiled_memcpy: Rework the RGBA -> BGRA mem_copy functions
This splits the two copy functions into three: One for unaligned copies,
one for aligned sources, and one for aligned destinations.  Thanks to the
previous commit, we are now guaranteed that the aligned ones will *only*
operate on aligned memory so they should be safe.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93962
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-04-08 12:09:15 -07:00
Jason Ekstrand
f6f54a29ca i965/tiled_memcopy: Add aligned mem_copy parameters to the [de]tiling functions
Each of the [de]tiling functions has three mem_copy calls:

 1) Left edge to tile boundary
 2) Tile boundary to tile boundary in a loop
 3) Tile boundary to right edge

Copies 2 and 3 start at a tile edge so the pointer to tiled memory is
guaranteed to be at least 16-byte aligned.  Copy 1, on the other hand,
starts at some arbitrary place in the tile so it doesn't have any such
alignment guarantees.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-04-08 12:08:51 -07:00
Ben Widawsky
e5295b5fb4 i965: Check eu/subslices are > 0
Now that the check is restricted to gen8+, we should always get back a non-zero
positive value for the EU and subslice counts.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-08 11:52:29 -07:00
Ben Widawsky
cc01b63d73 i965: Fix eu/subslice warning
Older gen platforms do not actually return a value for sublice and eu total
(IMO, confusingly) they return -ENODEV. This patch defers the SSEU setup until
we have the actual GPU generation to avoid useless warnings when running on
older platforms with older kernels.

Reported-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-08 11:52:29 -07:00
Ben Widawsky
4213b00e30 i965: Extract SSEU configuration info
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-08 11:51:01 -07:00
Brian Paul
4420f189b6 st/mesa: fix glReadBuffer() assertion failure
If the first call in a GL app is glReadPixels(GL_FRONT) we'd fail the
assert(st->ctx->FragmentProgram._Current) at st_atom_shader.c:114 in
update_fp().

This is because we were calling st_validate_state() without first
updating Mesa state with _mesa_update_state().

The regression came from commit 83b589301f "st/mesa: fix
frontbuffer glReadPixels regressions".

The new piglit gl-1.0-simple-readbuffer test exercises this.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-04-08 09:49:05 -06:00
Thomas Hindoe Paaboel Andersen
b9855dcdf7 st/va: avoid dereference after free in vlVaDestroyImage
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
2016-04-08 06:57:17 +01:00
Jason Ekstrand
e26a978773 Merge remote-tracking branch 'public/master' into vulkan 2016-04-07 16:56:34 -07:00
Jason Ekstrand
15895bf777 i965/fs: Use the scale helper in surface_builder
As requested by Curro
2016-04-07 16:49:09 -07:00
Marek Olšák
1cd19ebc4a radeonsi: do per-pixel clipping based on viewport states
In other words, vport scissors are derived from viewport states.
If the scissor test is enabled, the intersection of both is used.

The guard band will disable clipping, so we have to clip per-pixel.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-04-08 00:23:05 +02:00
Samuel Pitoiset
059308db84 nv50/ir: do not try to attach JOIN ops to ATOM
This might result in an INVALID_OPCODE dmesg error in case a join is
attached to an atomic operation.

Spotted with arb_shader_image_load_store-host-mem-barrier on GK104.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2016-04-07 23:10:26 +02:00
Nicolai Hähnle
2abe4f8d7d radeonsi: raise number of samplers per shader to 32
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94835
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-07 13:15:06 -05:00
Nicolai Hähnle
9d2693f58a radeonsi: expand the compressed color and depth texture masks to 64 bits
This is in preparation of raising the number of exposed sampler views to 32
bits, which will raise the total number of sampler views to 33 for the
polygon stipple texture. That texture should never be compressed (and it's
certainly not a depth texture), but this approach seems cleaner to me than
special-casing the last slot in all affected code paths.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-07 13:15:06 -05:00
Nicolai Hähnle
f270067ef9 radeonsi: replace magic 16 by SI_NUM_USER_SAMPLERS
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-07 13:15:06 -05:00
Nicolai Hähnle
f09036f6c0 gallium: raise PIPE_MAX_SAMPLERS to 32
The previous value of 18 was motivated by having drivers that want to expose
16 samplers but also use some additional samplers for internal use. Raising
the value even higher isn't going to hurt that case.

On the other hand, some drivers actually use PIPE_MAX_SAMPLERS as the number
of samplers they expose externally, so raising this number above 32 is fragile
(because several places in the code use bitfields, and tracking down and
widening all of them is prone to miss some case).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-07 13:15:05 -05:00
Nicolai Hähnle
84c4d069ac st/glsl_to_tgsi: make samplers_used an uint32_t (v2)
It is used as a bitfield, so it seems cleaner to keep it unsigned.

The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

v2: add an assert for bitfield size and use 1u << idx

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2016-04-07 13:15:05 -05:00
Nicolai Hähnle
4bfcc86bf9 tgsi/scan: add an assert for the size of the samplers_declared bitfield
The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-07 13:15:05 -05:00
Nicolai Hähnle
cc39879989 draw/aaline: stronger guard against no free samplers (v2)
Line anti-aliasing will fail when there is no free sampler available. Make
the corresponding guard more robust in preparation of raising
PIPE_MAX_SAMPLERS to 32.

The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

v2: add an assert for bitfield size and use 1u << idx

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2016-04-07 13:15:05 -05:00