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420 commits

Author SHA1 Message Date
Sonny Jiang
084cf3b966 radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang
ce1d72609d radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang
4de328da07 radeonsi:optimizing SET_CONTEXT_REG for shaders PS 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang
f243980f2c radeonsi:optimizing SET_CONTEXT_REG for shaders VS 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang
4052624398 radeonsi:optimizing SET_CONTEXT_REG for shaders GS 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 19:04:13 -04:00
Sonny Jiang
eeb9170599 radeonsi: optimizing SET_CONTEXT_REG for shaders ES 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-10-05 17:53:52 -04:00
Marek Olšák
0b062f0419 radeonsi: don't set the VS prolog key for the blit VS 2018-10-02 12:21:49 -04:00
Marek Olšák
5693ca865d radeonsi: bump MAX_GS_INVOCATIONS 
same as the closed driver

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-08-23 16:56:17 -04:00
Marek Olšák
ac72a6bd0b radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2018-08-14 21:20:31 -04:00
Marek Olšák
86b52d4236 radeonsi: reduce LDS stalls by 40% for tessellation 
40% is the decrease in the LGKM counter (which includes SMEM too)
for the GFX9 LSHS stage.

This will make the LDS size slightly larger, but I wasn't able to increase
the patch stride without corruption, so I'm increasing the vertex stride.
 2018-07-23 20:23:52 -04:00
Sonny Jiang
c6737756ad radeonsi: emit_spi_map packets optimization 
v2: marek: remove an empty line before break;
    rename reg_val_seq -> spi_ps_input_cntl
    "type * x" -> "type *x"

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2018-07-20 13:50:26 -04:00
Dave Airlie
0eb65b4944 radeonsi: rename si_compiler -> ac_llvm_compiler 
As precursor to moving init to common code, just rename the struct
and move it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-07-04 05:31:32 +10:00
Marek Olšák
1542169a4a radeonsi: enable shader caching for compute shaders 
Compute shaders were not using the shader cache.
 2018-06-28 22:27:25 -04:00
Marek Olšák
d13f240269 radeonsi: unify duplicated code for initial shader compilation 2018-06-28 22:27:25 -04:00
Marek Olšák
f154555733 radeonsi: clean up passing the is_monolithic flag for compilation 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
6703fec58c amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbuf 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-06-19 13:08:50 -04:00
Marek Olšák
22e994bb75 radeonsi: assume that rasterizer state is non-NULL in draw_vbo 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-06-13 22:00:36 -04:00
Marek Olšák
f3b3ee6974 radeonsi: micro-optimize prim checking and fix guardband with lines+adjacency 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-06-13 22:00:34 -04:00
Marek Olšák
28ee825e19 radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gs 
same as amdvlk.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-06-13 22:00:23 -04:00
Marek Olšák
99e0ba6868 radeonsi: record CLIPVERTEX output usage properly for compatibility profiles 
This was missed when adding CLIPVERTEX support into GS & tess.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-06-13 22:00:20 -04:00
Marek Olšák
2f65c67043 radeonsi: fix passing gl_ClipVertex for GS and tess 
Also add the fprintf call.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-25 16:46:00 -04:00
Marek Olšák
a7d61c0753 radeonsi: fix color inputs/outputs for GS and tess 
GS is tested, tessellation is untested.

Have outputs_written_before_ps for HW VS and outputs_written for other
stages. The reason is that COLOR and BCOLOR alias for HW VS, which
drives elimination of VS outputs based on PS inputs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-25 16:46:00 -04:00
Marek Olšák
92ea9329e5 radeonsi: fix incorrect parentheses around VS-PS varying elimination 
I don't know if it caused issues.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-25 16:46:00 -04:00
Marek Olšák
07e02c8617 radeonsi: round ps_iter_samples in set_min_samples 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-24 13:41:57 -04:00
Marek Olšák
87eb597758 radeonsi: add struct si_compiler containing LLVMTargetMachineRef 
It will contain more variables.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák
6fadfc01c6 radeonsi: use r600_resource() typecast helper 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák
3160ee876a radeonsi: remove unused atom parameter from si_atom::emit 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák
e395475096 radeonsi: remove function si_init_atom 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák
639b673fc3 radeonsi: don't use an indirect table for state atoms 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák
9054799b39 radeonsi: rename r600_atom -> si_atom 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-27 17:56:04 -04:00
Marek Olšák
60299e9abe radeonsi: don't emit partial flushes for internal CS flushes only 
Tested-by: Benedikt Schemmer <ben@besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-04-16 16:58:10 -04:00
Marek Olšák
6a93441295 radeonsi: remove r600_common_context 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
5777488406 radeonsi: move r600_cs.h contents into si_pipe.h, si_build_pm4.h 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
72e9e98076 radeonsi: move and rename R600_ERR out of r600_pipe_common.h 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
5f1cddde78 radeonsi: move definitions out of r600_pipe_common.h 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
c424f86180 radeonsi: use si_context instead of pipe_context in parameters pt1 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
4c5efc40f4 radeonsi: update copyrights 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
95bc30275b radeonsi: switch radeon_add_to_buffer_list parameter to si_context 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
2b70dd8c8a radeonsi: flatten / remove struct r600_ring 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
17e8f1608e radeonsi: call CS flush functions directly whenever possible 
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-04-05 15:34:58 -04:00
Marek Olšák
0669dca9c0 radeonsi: skip DCC render feedback checking if color writes are disabled 2018-04-05 15:34:58 -04:00
Marek Olšák
2be6143032 radeonsi: implement GL_KHR_blend_equation_advanced 
MSAA is supported using sample shading. Layered rendering and all texture
targets are also supported.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-04-02 13:55:25 -04:00
Marek Olšák
9b7db12815 radeonsi: remove chip_class parameter from si_lower_nir 
We can get it from si_screen.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
 2018-03-08 14:58:16 -05:00
Marek Olšák
2e30268877 radeonsi: mask out high VM address bits in registers where needed 2018-03-07 13:55:35 -05:00
Timothy Arceri
70190a6567 radeonsi/nir: call ac_lower_indirect_derefs() 
Fixes piglit tests:
tests/spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec3-index-rd.shader_test
tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-03-05 14:09:23 +11:00
Timothy Arceri
561503e3bd radeonsi: add chip class to compiler_ctx_state 
This will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-03-05 14:09:23 +11:00
Marek Olšák
8799eaed99 radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers 
The effect of the last 13 commits on user SGPR counts:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-26 12:01:19 +01:00
Marek Olšák
3fa7a59d69 radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR input 
so that it can be removed and replaced with inline VBO descriptors,
and the pointer can be packed in unused bits of VBO descriptors.
This also removes the pointer from merged TES-GS where it's useless.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-26 12:01:08 +01:00
Marek Olšák
2d03c4cac8 radeonsi: move tess ring address into TCS_OUT_LAYOUT, removes 2 TCS user SGPRs 
TCS_OUT_LAYOUT has 13 unused bits. That's enough for a 32-bit address
aligned to 512KB. Hey, it's a 13-bit pointer!

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-24 23:08:29 +01:00
Marek Olšák
fca7dee9c6 radeonsi: put both tessellation rings into 1 buffer 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-02-24 23:08:28 +01:00