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radeonsi/nir: call ac_lower_indirect_derefs()

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Fixes piglit tests:
tests/spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec3-index-rd.shader_test
tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Timothy Arceri 2018-03-05 12:06:01 +11:00
parent 561503e3bd
commit 70190a6567
4 changed files with 6 additions and 4 deletions
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2
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -107,7 +107,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
sel.nir = program->ir.nir;
si_nir_scan_shader(sel.nir, &sel.info);
si_lower_nir(&sel);
si_lower_nir(&sel, program->compiler_ctx_state.chip_class);
}

2
src/gallium/drivers/radeonsi/si_shader.h
View file

@ -674,7 +674,7 @@ void si_nir_scan_shader(const struct nir_shader *nir,
void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
const struct tgsi_shader_info *info,
struct tgsi_tessctrl_info *out);
void si_lower_nir(struct si_shader_selector *sel);
void si_lower_nir(struct si_shader_selector *sel, enum chip_class chip_class);
/* Inline helpers. */

4
src/gallium/drivers/radeonsi/si_shader_nir.c
View file

@ -623,7 +623,7 @@ void si_nir_scan_shader(const struct nir_shader *nir,
* selector is created.
*/
void
si_lower_nir(struct si_shader_selector* sel)
si_lower_nir(struct si_shader_selector* sel, enum chip_class chip_class)
{
/* Adjust the driver location of inputs and outputs. The state tracker
* interprets them as slots, while the ac/nir backend interprets them
@ -673,6 +673,8 @@ si_lower_nir(struct si_shader_selector* sel)
};
NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
ac_lower_indirect_derefs(sel->nir, chip_class);
bool progress;
do {
progress = false;

2
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -1999,7 +1999,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
si_nir_scan_shader(sel->nir, &sel->info);
si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
si_lower_nir(sel);
si_lower_nir(sel, sctx->b.chip_class);
}
sel->type = sel->info.processor;