fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-20 20:50:44 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radeonsi: use r600_resource() typecast helper

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2018-04-08 21:52:05 -04:00
parent 3160ee876a
commit 6fadfc01c6
19 changed files with 80 additions and 78 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/gallium/drivers/radeon/radeon_vcn_dec.c
View file

@ -853,8 +853,8 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->bsd_size = align(dec->bs_size, 128);
decode->dpb_size = dec->dpb.res->buf->size;
decode->dt_size =
((struct r600_resource *)((struct vl_video_buffer *)target)->resources[0])->buf->size +
((struct r600_resource *)((struct vl_video_buffer *)target)->resources[1])->buf->size;
r600_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
r600_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
decode->sct_size = 0;
decode->sc_coeff_size = 0;

5
src/gallium/drivers/radeon/radeon_video.c
View file

@ -63,9 +63,8 @@ bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer
* able to move buffers around individually, so request a
* non-sub-allocated buffer.
*/
buffer->res = (struct r600_resource *)
pipe_buffer_create(screen, PIPE_BIND_SHARED,
usage, size);
buffer->res = r600_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED,
usage, size));
return buffer->res != NULL;
}

20
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -478,9 +478,9 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx,
struct r600_resource *staging;
assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
staging = (struct r600_resource*) pipe_buffer_create(
staging = r600_resource(pipe_buffer_create(
ctx->screen, 0, PIPE_USAGE_STAGING,
box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT));
box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT)));
if (staging) {
/* Copy the VRAM buffer to the staging buffer. */
sctx->dma_copy(ctx, &staging->b.b, 0,
@ -648,11 +648,9 @@ static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
return &rbuffer->b.b;
}
struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags,
unsigned usage,
unsigned size,
unsigned alignment)
struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned alignment)
{
struct pipe_resource buffer;
@ -669,6 +667,14 @@ struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
return si_buffer_create(screen, &buffer, alignment);
}
struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned alignment)
{
return r600_resource(pipe_aligned_buffer_create(screen, flags, usage,
size, alignment));
}
static struct pipe_resource *
si_buffer_from_user_memory(struct pipe_screen *screen,
const struct pipe_resource *templ,

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -46,7 +46,7 @@ static void si_alloc_separate_cmask(struct si_screen *sscreen,
if (!rtex->cmask.size)
return;
rtex->cmask_buffer = (struct r600_resource *)
rtex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,

14
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -356,11 +356,11 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
if (scratch_bo_size < scratch_needed) {
r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
sctx->compute_scratch_buffer = (struct r600_resource*)
sctx->compute_scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed, 256);
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed, 256);
if (!sctx->compute_scratch_buffer)
return false;
@ -703,7 +703,7 @@ static void si_setup_tgsi_grid(struct si_context *sctx,
int i;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource *)info->indirect,
r600_resource(info->indirect),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
for (i = 0; i < 3; ++i) {
@ -774,7 +774,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx,
uint64_t base_va = r600_resource(info->indirect)->gpu_address;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource *)info->indirect,
r600_resource(info->indirect),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
@ -877,7 +877,7 @@ static void si_launch_grid(
/* Global buffers */
for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
struct r600_resource *buffer =
(struct r600_resource*)program->global_buffers[i];
r600_resource(program->global_buffers[i]);
if (!buffer) {
continue;
}

6
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -186,11 +186,11 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
/* This must be done after need_cs_space. */
if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource*)dst,
r600_resource(dst),
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
if (src)
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource*)src,
r600_resource(src),
RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
}
@ -380,7 +380,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
if (!sctx->scratch_buffer ||
sctx->scratch_buffer->b.b.width0 < scratch_size) {
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = (struct r600_resource*)
sctx->scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,

24
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -262,7 +262,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
resource = &tex->flushed_depth_texture->resource.b.b;
}
rres = (struct r600_resource*)resource;
rres = r600_resource(resource);
priority = si_get_sampler_view_priority(rres);
radeon_add_to_gfx_buffer_list_check_mem(sctx, rres, usage, priority,
@ -673,7 +673,7 @@ si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
static void
si_mark_image_range_valid(const struct pipe_image_view *view)
{
struct r600_resource *res = (struct r600_resource *)view->resource;
struct r600_resource *res = r600_resource(view->resource);
assert(res && res->b.b.target == PIPE_BUFFER);
@ -690,7 +690,7 @@ static void si_set_shader_image_desc(struct si_context *ctx,
struct si_screen *screen = ctx->screen;
struct r600_resource *res;
res = (struct r600_resource *)view->resource;
res = r600_resource(view->resource);
if (res->b.b.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
@ -786,7 +786,7 @@ static void si_set_shader_image(struct si_context *ctx,
return;
}
res = (struct r600_resource *)view->resource;
res = r600_resource(view->resource);
if (&images->views[slot] != view)
util_copy_image_view(&images->views[slot], view);
@ -1077,7 +1077,7 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
continue;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource*)sctx->vertex_buffer[vb].buffer.resource,
r600_resource(sctx->vertex_buffer[vb].buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
@ -1137,7 +1137,7 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
uint32_t *desc = &ptr[i*4];
vb = &sctx->vertex_buffer[vbo_index];
rbuffer = (struct r600_resource*)vb->buffer.resource;
rbuffer = r600_resource(vb->buffer.resource);
if (!rbuffer) {
memset(desc, 0, 16);
continue;
@ -1163,7 +1163,7 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource*)vb->buffer.resource,
r600_resource(vb->buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
}
}
@ -1262,7 +1262,7 @@ static void si_set_constant_buffer(struct si_context *sctx,
buffers->buffers[slot] = buffer;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
(struct r600_resource*)buffer,
r600_resource(buffer),
buffers->shader_usage_constbuf,
buffers->priority_constbuf, true);
buffers->enabled_mask |= 1u << slot;
@ -1344,7 +1344,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
continue;
}
buf = (struct r600_resource *)sbuffer->buffer;
buf = r600_resource(sbuffer->buffer);
va = buf->gpu_address + sbuffer->buffer_offset;
desc[0] = va;
@ -1474,7 +1474,7 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot,
pipe_resource_reference(&buffers->buffers[slot], buffer);
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource*)buffer,
r600_resource(buffer),
buffers->shader_usage, buffers->priority);
buffers->enabled_mask |= 1u << slot;
} else {
@ -1599,7 +1599,7 @@ static void si_reset_buffer_resources(struct si_context *sctx,
sctx->descriptors_dirty |= 1u << descriptors_idx;
radeon_add_to_gfx_buffer_list_check_mem(sctx,
(struct r600_resource *)buf,
r600_resource(buf),
usage, priority, true);
}
}
@ -2569,7 +2569,7 @@ static void si_make_image_handle_resident(struct pipe_context *ctx,
img_handle = (struct si_image_handle *)entry->data;
view = &img_handle->view;
res = (struct r600_resource *)view->resource;
res = r600_resource(view->resource);
if (resident) {
if (res->b.b.target != PIPE_BUFFER) {

4
src/gallium/drivers/radeonsi/si_dma.c
View file

@ -37,8 +37,8 @@ static void si_dma_copy_buffer(struct si_context *ctx,
{
struct radeon_winsys_cs *cs = ctx->dma_cs;
unsigned i, ncopy, count, max_size, sub_cmd, shift;
struct r600_resource *rdst = (struct r600_resource*)dst;
struct r600_resource *rsrc = (struct r600_resource*)src;
struct r600_resource *rdst = r600_resource(dst);
struct r600_resource *rsrc = r600_resource(src);
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping

5
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -179,9 +179,8 @@ static void si_begin_gfx_cs_debug(struct si_context *ctx)
pipe_reference_init(&ctx->current_saved_cs->reference, 1);
ctx->current_saved_cs->trace_buf = (struct r600_resource*)
pipe_buffer_create(ctx->b.screen, 0,
PIPE_USAGE_STAGING, 8);
ctx->current_saved_cs->trace_buf = r600_resource(
pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
if (!ctx->current_saved_cs->trace_buf) {
free(ctx->current_saved_cs);
ctx->current_saved_cs = NULL;

18
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -367,9 +367,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
if (sctx->chip_class == CIK ||
sctx->chip_class == VI ||
sctx->chip_class == GFX9) {
sctx->eop_bug_scratch = (struct r600_resource*)
pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * sscreen->info.num_render_backends);
sctx->eop_bug_scratch = r600_resource(
pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * sscreen->info.num_render_backends));
if (!sctx->eop_bug_scratch)
goto fail;
}
@ -438,10 +438,10 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
if (!sctx->border_color_table)
goto fail;
sctx->border_color_buffer = (struct r600_resource*)
sctx->border_color_buffer = r600_resource(
pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
sizeof(*sctx->border_color_table)));
if (!sctx->border_color_buffer)
goto fail;
@ -475,8 +475,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->sample_mask = 0xffff;
if (sctx->chip_class >= GFX9) {
sctx->wait_mem_scratch = (struct r600_resource*)
pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
sctx->wait_mem_scratch = r600_resource(
pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
if (!sctx->wait_mem_scratch)
goto fail;
@ -497,8 +497,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
if (sctx->chip_class == CIK) {
sctx->null_const_buf.buffer =
si_aligned_buffer_create(screen,
SI_RESOURCE_FLAG_32BIT,
pipe_aligned_buffer_create(screen,
SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT, 16,
sctx->screen->info.tcc_cache_line_size);
if (!sctx->null_const_buf.buffer)

19
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1084,11 +1084,12 @@ void si_init_resource_fields(struct si_screen *sscreen,
uint64_t size, unsigned alignment);
bool si_alloc_resource(struct si_screen *sscreen,
struct r600_resource *res);
struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags,
unsigned usage,
unsigned size,
unsigned alignment);
struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned alignment);
struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
unsigned flags, unsigned usage,
unsigned size, unsigned alignment);
void si_replace_buffer_storage(struct pipe_context *ctx,
struct pipe_resource *dst,
struct pipe_resource *src);
@ -1316,12 +1317,10 @@ si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
static inline void
si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
{
struct r600_resource *res = (struct r600_resource *)r;
if (res) {
if (r) {
/* Add memory usage for need_gfx_cs_space */
sctx->vram += res->vram_usage;
sctx->gtt += res->gart_usage;
sctx->vram += r600_resource(r)->vram_usage;
sctx->gtt += r600_resource(r)->gart_usage;
}
}

2
src/gallium/drivers/radeonsi/si_pm4.c
View file

@ -167,7 +167,7 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx,
r600_resource_reference(&state->indirect_buffer, NULL);
/* TODO: this hangs with 1024 or higher alignment on GFX9. */
state->indirect_buffer = (struct r600_resource*)
state->indirect_buffer =
si_aligned_buffer_create(screen, 0,
PIPE_USAGE_DEFAULT, aligned_ndw * 4,
256);

6
src/gallium/drivers/radeonsi/si_query.c
View file

@ -530,9 +530,9 @@ static struct r600_resource *si_new_query_buffer(struct si_screen *sscreen,
* being written by the gpu, hence staging is probably a good
* usage pattern.
*/
struct r600_resource *buf = (struct r600_resource*)
struct r600_resource *buf = r600_resource(
pipe_buffer_create(&sscreen->b, 0,
PIPE_USAGE_STAGING, buf_size);
PIPE_USAGE_STAGING, buf_size));
if (!buf)
return NULL;
@ -1742,7 +1742,7 @@ static void si_query_hw_get_result_resource(struct si_context *sctx,
ssbo[2].buffer_offset = offset;
ssbo[2].buffer_size = 8;
((struct r600_resource *)resource)->TC_L2_dirty = true;
r600_resource(resource)->TC_L2_dirty = true;
}
sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);

3
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -5352,8 +5352,7 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
assert(!epilog || !epilog->rodata_size);
r600_resource_reference(&shader->bo, NULL);
shader->bo = (struct r600_resource*)
si_aligned_buffer_create(&sscreen->b,
shader->bo = si_aligned_buffer_create(&sscreen->b,
sscreen->cpdma_prefetch_writes_memory ?
0 : SI_RESOURCE_FLAG_READ_ONLY,
PIPE_USAGE_IMMUTABLE,

2
src/gallium/drivers/radeonsi/si_state.c
View file

@ -3852,7 +3852,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
/* Buffer resource. */
if (texture->target == PIPE_BUFFER) {
si_make_buffer_descriptor(sctx->screen,
(struct r600_resource *)texture,
r600_resource(texture),
state->format,
state->u.buf.offset,
state->u.buf.size,

6
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -720,7 +720,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
index_va = r600_resource(indexbuf)->gpu_address + index_offset;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource *)indexbuf,
r600_resource(indexbuf),
RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
} else {
/* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
@ -743,7 +743,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, indirect_va >> 32);
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
(struct r600_resource *)indirect->buffer,
r600_resource(indirect->buffer),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
@ -773,7 +773,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
if (indirect->indirect_draw_count) {
struct r600_resource *params_buf =
(struct r600_resource *)indirect->indirect_draw_count;
r600_resource(indirect->indirect_draw_count);
radeon_add_to_buffer_list(
sctx, sctx->gfx_cs, params_buf,

8
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -2720,7 +2720,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
if (update_esgs) {
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
si_aligned_buffer_create(sctx->b.screen,
pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
esgs_ring_size, alignment);
@ -2731,7 +2731,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
if (update_gsvs) {
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
si_aligned_buffer_create(sctx->b.screen,
pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, alignment);
@ -2972,7 +2972,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
/* Create a bigger scratch buffer */
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = (struct r600_resource*)
sctx->scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
@ -3009,7 +3009,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
/* The address must be aligned to 2^19, because the shader only
* receives the high 13 bits.
*/
sctx->tess_rings = si_aligned_buffer_create(sctx->b.screen,
sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT,
sctx->screen->tess_offchip_ring_size +

4
src/gallium/drivers/radeonsi/si_state_streamout.c
View file

@ -43,7 +43,7 @@ si_create_so_target(struct pipe_context *ctx,
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_streamout_target *t;
struct r600_resource *rbuffer = (struct r600_resource*)buffer;
struct r600_resource *rbuffer = r600_resource(buffer);
t = CALLOC_STRUCT(si_streamout_target);
if (!t) {
@ -201,7 +201,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
pipe_resource_reference(&buffers->buffers[bufidx],
buffer);
radeon_add_to_gfx_buffer_list_check_mem(sctx,
(struct r600_resource*)buffer,
r600_resource(buffer),
buffers->shader_usage,
RADEON_PRIO_SHADER_RW_BUFFER,
true);

6
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -691,7 +691,7 @@ static boolean si_texture_get_handle(struct pipe_screen* screen,
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct si_context *sctx;
struct r600_resource *res = (struct r600_resource*)resource;
struct r600_resource *res = r600_resource(resource);
struct r600_texture *rtex = (struct r600_texture*)resource;
struct radeon_bo_metadata metadata;
bool update_metadata = false;
@ -1789,7 +1789,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
&trans->b.b.layer_stride);
}
trans->staging = (struct r600_resource*)staging_depth;
trans->staging = &staging_depth->resource;
buf = trans->staging;
} else if (use_staging_texture) {
struct pipe_resource resource;
@ -2273,7 +2273,7 @@ void vi_separate_dcc_try_enable(struct si_context *sctx,
tex->dcc_separate_buffer = tex->last_dcc_separate_buffer;
tex->last_dcc_separate_buffer = NULL;
} else {
tex->dcc_separate_buffer = (struct r600_resource*)
tex->dcc_separate_buffer =
si_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,