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radeonsi: move and rename R600_ERR out of r600_pipe_common.h
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
parent
076afb4f0e
commit
72e9e98076
6 changed files with 19 additions and 19 deletions
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@ -521,7 +521,4 @@ vi_dcc_enabled(struct r600_texture *tex, unsigned level)
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return tex->dcc_offset && level < tex->surface.num_dcc_levels;
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}
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#define R600_ERR(fmt, args...) \
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fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
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#endif
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@ -868,13 +868,13 @@ void si_texture_get_fmask_info(struct si_screen *sscreen,
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bpe = 4;
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break;
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default:
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R600_ERR("Invalid sample count for FMASK allocation.\n");
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PRINT_ERR("Invalid sample count for FMASK allocation.\n");
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return;
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}
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if (sscreen->ws->surface_init(sscreen->ws, &templ, flags, bpe,
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RADEON_SURF_MODE_2D, &fmask)) {
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R600_ERR("Got error in surface_init while allocating FMASK.\n");
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PRINT_ERR("Got error in surface_init while allocating FMASK.\n");
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return;
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}
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@ -1573,7 +1573,7 @@ bool si_init_flushed_depth_texture(struct pipe_context *ctx,
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*flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
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if (*flushed_depth_texture == NULL) {
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R600_ERR("failed to create temporary texture to hold flushed depth\n");
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PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
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return false;
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}
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return true;
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@ -1735,7 +1735,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
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si_init_temp_resource_from_box(&resource, texture, box, level, 0);
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if (!si_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
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R600_ERR("failed to create temporary texture to hold untiled copy\n");
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PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
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FREE(trans);
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return NULL;
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}
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@ -1743,7 +1743,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
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if (usage & PIPE_TRANSFER_READ) {
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struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
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if (!temp) {
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R600_ERR("failed to create a temporary depth texture\n");
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PRINT_ERR("failed to create a temporary depth texture\n");
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FREE(trans);
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return NULL;
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}
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@ -1762,7 +1762,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
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/* XXX: only readback the rectangle which is being mapped? */
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/* XXX: when discard is true, no need to read back from depth texture */
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if (!si_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
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R600_ERR("failed to create temporary texture to hold untiled copy\n");
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PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
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FREE(trans);
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return NULL;
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}
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@ -1792,7 +1792,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
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/* Create the temporary texture. */
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staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
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if (!staging) {
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R600_ERR("failed to create temporary texture to hold untiled copy\n");
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PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
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FREE(trans);
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return NULL;
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}
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@ -1063,4 +1063,7 @@ static inline unsigned si_get_total_colormask(struct si_context *sctx)
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return colormask;
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}
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#define PRINT_ERR(fmt, args...) \
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fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
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#endif
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@ -69,7 +69,7 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
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reg -= CIK_UCONFIG_REG_OFFSET;
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} else {
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R600_ERR("Invalid register offset %08x!\n", reg);
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PRINT_ERR("Invalid register offset %08x!\n", reg);
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return;
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}
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@ -293,7 +293,7 @@ static uint32_t si_translate_blend_function(int blend_func)
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case PIPE_BLEND_MAX:
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return V_028780_COMB_MAX_DST_SRC;
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default:
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R600_ERR("Unknown blend function %d\n", blend_func);
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PRINT_ERR("Unknown blend function %d\n", blend_func);
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assert(0);
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break;
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}
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@ -342,7 +342,7 @@ static uint32_t si_translate_blend_factor(int blend_fact)
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case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
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return V_028780_BLEND_INV_SRC1_ALPHA;
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default:
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R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
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PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
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assert(0);
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break;
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}
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@ -1133,7 +1133,7 @@ static uint32_t si_translate_stencil_op(int s_op)
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case PIPE_STENCIL_OP_INVERT:
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return V_02842C_STENCIL_INVERT;
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default:
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R600_ERR("Unknown stencil op %d", s_op);
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PRINT_ERR("Unknown stencil op %d", s_op);
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assert(0);
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break;
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}
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@ -2143,7 +2143,7 @@ static boolean si_is_format_supported(struct pipe_screen *screen,
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unsigned retval = 0;
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if (target >= PIPE_MAX_TEXTURE_TYPES) {
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R600_ERR("r600: unsupported texture type %d\n", target);
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PRINT_ERR("r600: unsupported texture type %d\n", target);
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return false;
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}
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@ -2381,7 +2381,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
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format = si_translate_colorformat(surf->base.format);
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if (format == V_028C70_COLOR_INVALID) {
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R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
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PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
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}
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assert(format != V_028C70_COLOR_INVALID);
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swap = si_translate_colorswap(surf->base.format, false);
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@ -2513,7 +2513,7 @@ static void si_init_depth_surface(struct si_context *sctx,
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assert(format != V_028040_Z_INVALID);
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if (format == V_028040_Z_INVALID)
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R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
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PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
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surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
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S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
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@ -2934,7 +2934,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
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constbuf.user_buffer = sctx->sample_locations_16x;
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break;
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default:
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R600_ERR("Requested an invalid number of samples %i.\n",
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PRINT_ERR("Requested an invalid number of samples %i.\n",
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sctx->framebuffer.nr_samples);
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assert(0);
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}
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@ -1511,7 +1511,7 @@ static void si_build_shader_variant(struct si_shader *shader,
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r = si_shader_create(sscreen, tm, shader, debug);
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if (unlikely(r)) {
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R600_ERR("Failed to build shader variant (type=%u) %d\n",
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PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
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sel->type, r);
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shader->compilation_failed = true;
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return;
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