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Author	SHA1	Message	Date
Alyssa Rosenzweig	20e2267be5	hk: readvertise required bgra4 format ... spec dealt with. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	ca255cb703	hk: always lower bindless samplers ... oddly only a single CTS case hits this. dEQP-VK.subgroups.uniform_descriptor_indexing.combined_image_sampler Fixes: 642c6c6f62 ("hk,agx: promote bindless samplers") Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	20bf4a28a2	hk: use amul instead of imul ... lets use do our address arithmetic tricks. preambles helped. Totals: MaxWaves: 53066688 -> 53068928 (+0.00%); split: +0.01%, -0.01% Instrs: 23846587 -> 23794159 (-0.22%); split: -0.24%, +0.02% CodeSize: 170248964 -> 169876998 (-0.22%); split: -0.24%, +0.02% Spills: 66570 -> 66401 (-0.25%); split: -0.53%, +0.27% Fills: 44068 -> 43879 (-0.43%); split: -0.98%, +0.55% Scratch: 404374 -> 403894 (-0.12%); split: -0.18%, +0.06% ALU: 18567924 -> 18510790 (-0.31%); split: -0.33%, +0.02% FSCIB: 18512622 -> 18455472 (-0.31%); split: -0.33%, +0.02% IC: 5255884 -> 5279176 (+0.44%); split: -0.11%, +0.56% GPRs: 3833699 -> 3833127 (-0.01%); split: -0.05%, +0.04% Uniforms: 10531468 -> 10528625 (-0.03%); split: -0.03%, +0.00% Preamble instrs: 10435998 -> 10289152 (-1.41%); split: -1.43%, +0.02% Totals from 6482 (12.00% of 54019) affected shaders: MaxWaves: 5819712 -> 5821952 (+0.04%); split: +0.09%, -0.05% Instrs: 5777505 -> 5725077 (-0.91%); split: -1.01%, +0.10% CodeSize: 42654844 -> 42282878 (-0.87%); split: -0.97%, +0.09% Spills: 23065 -> 22896 (-0.73%); split: -1.53%, +0.79% Fills: 7927 -> 7738 (-2.38%); split: -5.46%, +3.08% Scratch: 310148 -> 309668 (-0.15%); split: -0.23%, +0.08% ALU: 4424867 -> 4367733 (-1.29%); split: -1.39%, +0.10% FSCIB: 4424651 -> 4367501 (-1.29%); split: -1.39%, +0.10% IC: 1144594 -> 1167886 (+2.03%); split: -0.53%, +2.56% GPRs: 620494 -> 619922 (-0.09%); split: -0.33%, +0.24% Uniforms: 1622654 -> 1619811 (-0.18%); split: -0.20%, +0.02% Preamble instrs: 2119640 -> 1972794 (-6.93%); split: -7.03%, +0.10% Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	a60755c015	agx: use immediate load ts/ss forms ... Honeykrisp appreciates this. Funny looking fossil stats: Totals: Preamble instrs: 10638975 -> 10435998 (-1.91%); split: -1.91%, +0.00% Totals from 23612 (43.71% of 54019) affected shaders: Preamble instrs: 5104103 -> 4901126 (-3.98%); split: -3.98%, +0.00% Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	3a798e58e5	agx: add immediate load ts/ss encodings ... TellowKrinkle found this by experimentation. Seems to work great. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	e48d1ca349	agx: optimize imgwblk uniform ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	1ded5f55e8	agx: optimize txl LOD ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	2dd91b0d1c	agx: simplify block image store offset ... just make 32-bit offset. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	cbbc24a473	agx: fix dead phis ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:20 +00:00
Alyssa Rosenzweig	b9c2579ae0	nir: unmark 24b multiply as associative ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Suggested-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:19 +00:00
Alyssa Rosenzweig	076f245df8	nir: restrict associativity to binary operations ... mathemtically, associativity is only defined for binary operations. I have no idea what "associativity" would even mean for imad. I can kinda see the idea for iadd3 but iadd3 should not be formed until after reassociating adds so the point is moot. Unmark the "associative" ternary operations, and assert that associativity implies binary. nothing uses associativity yet, so this doesn't cause any functional change. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:19 +00:00
Alyssa Rosenzweig	e466b8735b	nir: introduce "inexact associative" property ... nothing currently uses the associative flag, but they will change soon. we need to stop incorrectly marking fmul/fadd/etc as associative, because they're not, but they almost are. distinguish these properties so we can correctly handle floating point rules without any opcode-based special casing. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:19 +00:00
Alyssa Rosenzweig	421d0e0953	nir: mark exact fmul in ldexp lowering ... this chain of fmul is deliberately chosen for floating point precision reasons, it needs to be exact, or else we might try to reassociate it and break subnormal handling. avoids regressing dEQP-VK.glsl.builtin.precision.ldexp_subnormals.* Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:18 +00:00
Alyssa Rosenzweig	ecfca8ec6f	util: crib SWAP macro from freedreno ... we have a bunch of copies across the tree, unify them. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>	2025-07-21 11:42:18 +00:00
Karol Herbst	7ce8369985	rusticl/queue: do not return event status errors on flush/finish ... Fixes random fails in the test_events userevents test as it sets an event to -1 and clFinish returned that error code making the test fail. Fixes: 3129fd8dcf ("rusticl/queue: check device error status") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36250>	2025-07-21 11:26:52 +00:00
David Rosca	566ea76d8e	radv/video: Support DRM format modifier tiling ... Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36192>	2025-07-21 10:56:34 +00:00
David Rosca	21573c3d2d	radeonsi/video: Use ac_modifier_supports_video ... Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36192>	2025-07-21 10:56:34 +00:00
David Rosca	e435ea78e8	ac/surface: Add ac_modifier_supports_video ... Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36192>	2025-07-21 10:56:34 +00:00
Mary Guillemard	cd71f212b0	panvk: Exposes robustBufferAccess2 on v11+ ... This works out of the box on v11+. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36198>	2025-07-21 10:36:16 +00:00
Mary Guillemard	621f334a4c	panvk: Wire robustness2 buffer info down to pan/bi ... Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36198>	2025-07-21 10:36:16 +00:00
Mary Guillemard	af5fb42080	panvk: Fix nullDescriptor for dynamic descriptors ... Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Fixes: a789867cb4 ("panvk/v10+: Implement nullDescriptor support") Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36198>	2025-07-21 10:36:16 +00:00
David Rosca	211dc09e0f	radv/video: Fix encode when using layered source image ... Found by inspection. Cc: mesa-stable Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36214>	2025-07-21 09:52:47 +00:00
Rhys Perry	d81add3dda	aco: optimize s_and(s_cselect, exec) ... fossil-db (navi21): Totals from 62 (0.08% of 79825) affected shaders: Instrs: 178887 -> 178745 (-0.08%) CodeSize: 942980 -> 942328 (-0.07%) Latency: 1274513 -> 1273653 (-0.07%) InvThroughput: 213862 -> 213774 (-0.04%); split: -0.04%, +0.00% SALU: 26446 -> 26301 (-0.55%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36005>	2025-07-21 08:27:01 +00:00
Rhys Perry	8fd5266b69	nir/divergence: ignore boolean phis for ignore_undef_if_phi_srcs ... The only user of this option (ACO) doesn't support this for boolean phis. fossil-db (navi21): Totals from 1208 (1.51% of 79825) affected shaders: Instrs: 826592 -> 823201 (-0.41%); split: -0.41%, +0.00% CodeSize: 4228296 -> 4224280 (-0.09%); split: -0.11%, +0.01% Latency: 3030803 -> 3028410 (-0.08%); split: -0.08%, +0.01% InvThroughput: 578588 -> 578693 (+0.02%); split: -0.00%, +0.02% VClause: 19500 -> 19494 (-0.03%) Copies: 60914 -> 57589 (-5.46%); split: -5.47%, +0.01% PreVGPRs: 50759 -> 50774 (+0.03%) VALU: 528582 -> 528671 (+0.02%); split: -0.00%, +0.02% SALU: 121134 -> 117646 (-2.88%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Backport-to: 25.1 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13455 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13509 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36005>	2025-07-21 08:27:01 +00:00
Rhys Perry	b2e5fc9451	aco/lower_phis: add bld_before_logical_end helper ... Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36005>	2025-07-21 08:27:01 +00:00
Samuel Pitoiset	49e49d7dde	radv: add RADV_DEBUG=novideo to disable all video extensions ... It's useful when video support has issues. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36186>	2025-07-21 07:20:12 +00:00
Samuel Pitoiset	af22d5c97d	radv: use vk_optimize_depth_stencil_state() for optimal settings ... For apps that aren't optimized. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36168>	2025-07-21 06:53:40 +00:00
Samuel Pitoiset	79c02a3388	radv: adjust conservative rasterization configuration on GFX12 ... PAL doesn't set these two registers either. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36196>	2025-07-21 06:26:48 +00:00
Sergi Blanch-Torne	9632c9b280	ci: disable Collabora's farm due to maintenance ... Planned downtime in the farm: * Start: 2025-07-21 07:00 UTC * End: 2025-07-21 13:00 UTC Signed-off-by: Sergi Blanch-Torne <sergi.blanch.torne@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35861>	2025-07-21 06:03:20 +00:00
Marek Olšák	09cc5f0c37	glsl: use pipe_screen::nir_options instead of NirOptions ... Perhaps the more interesting thing is that the GLSL compiler can now access pipe_screen for caps Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36094>	2025-07-21 00:18:21 +00:00
Marek Olšák	eba8f95805	mesa: use pipe_screen::nir_options instead of NirOptions ... Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36094>	2025-07-21 00:18:21 +00:00
Marek Olšák	613b58e88f	st/mesa: don't expect pipe_screen::nir_options to be NULL for supported shaders ... All drivers set non-NULL where needed I think. Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36094>	2025-07-21 00:18:21 +00:00
Marek Olšák	c1a939ca11	gallium: replace get_compiler_options with pipe_screen::nir_options ... Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36094>	2025-07-21 00:18:20 +00:00
Marek Olšák	a30f1fa7f0	gallium: make pipe_screen::finalize_nir return void ... The returned message was replaced by create_xx_state returning the message. Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36094>	2025-07-21 00:18:20 +00:00
Lucas Stach	5afcf93a59	etnaviv: use new shader range registers when icache is present ... As seen in the Vivante kernel driver context init, GPUs with the icache feature have a new set of states to specify the shader ranges. While the old state still seems to work, it limits the size of the shader that can be executed to 64K instructions. The new range states holds up to 20 bits according to the comment in the Vivante kernel driver, which allows up to 1M instructions. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>	2025-07-20 11:44:52 +00:00
Lucas Stach	534b948a9c	etnaviv: don't emit start/end PC states when unified instmem is present ... Cores with unified instruction memory get the start and end points of the shaders via the shader range registers. Don't emit the unnecessary START_PC and END_PC states on those cores. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>	2025-07-20 11:44:52 +00:00
Lucas Stach	a0d4418de3	etnaviv: update code steering bit when writing shader instructions ... When writing new shader instructions through the unified state area we must tell the GPU which caches to flush by setting the appropriate code steering bit. Failing to do this doesn't seem to have much of an effect when only loading shaders through the state memory, but when toggling between using icache (as in load shaders from memory) and loading instructions from the state area, this fixes severe corruption and GPU hangs due to old code being executed. Programming the steering bits is only needed for GPUs with either unified instruction or unified uniform states. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>	2025-07-20 11:44:51 +00:00
Lucas Stach	845e7c4426	etnaviv: stop touching code steering bits while updating uniforms ... Bit 0 of the SH_CONTROL register does not control uniform cache flushes so stop touching this bit when updating the uniforms. While it is harmless to change the bit at this time in the emit sequence, it's confusing and not needed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>	2025-07-20 11:44:51 +00:00
Lucas Stach	b093fa9dcf	etnaviv: Update headers from rnndb ... Update from rnndb commit 19bc9377a80a ("rnndb: rename UNIFORM_CACHE to CONTROL and document code cache flushing") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>	2025-07-20 11:44:51 +00:00
Konstantin Seurer	d59c22b6e1	radv/rt: Implement null acceleration structure in shader code ... The previous approach is broken with descriptor buffer capture/replay because the address off the dummy VA used can randomly change. Totals from 78 (20.58% of 379) affected shaders: Instrs: 3837275 -> 3839653 (+0.06%); split: -0.01%, +0.07% CodeSize: 20235104 -> 20251744 (+0.08%); split: -0.01%, +0.09% SpillSGPRs: 997 -> 1007 (+1.00%) Latency: 22305937 -> 22331551 (+0.11%); split: -0.03%, +0.15% InvThroughput: 4232313 -> 4237341 (+0.12%); split: -0.03%, +0.15% VClause: 97043 -> 97027 (-0.02%); split: -0.02%, +0.01% SClause: 72169 -> 72416 (+0.34%); split: -0.00%, +0.35% Copies: 321578 -> 322126 (+0.17%); split: -0.11%, +0.28% Branches: 110163 -> 110444 (+0.26%); split: -0.00%, +0.26% PreSGPRs: 7879 -> 7942 (+0.80%) VALU: 2155040 -> 2156425 (+0.06%); split: -0.02%, +0.09% SALU: 502292 -> 503078 (+0.16%); split: -0.00%, +0.16% Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36034>	2025-07-19 21:02:42 +00:00
Caio Oliveira	3c7dd0ccf1	brw: Make brw_builder() shader constructor use CFG if available ... Properly pick the end of the last block as a cursor. Also remove the default constructor since is not needed anymore. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34681>	2025-07-19 17:49:48 +00:00
Caio Oliveira	ab8af62745	brw: Use a builder to track position in lower_simd ... Removes brw_builder::at() since it is now unused, replaced by various other helpers. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34681>	2025-07-19 17:49:48 +00:00
Caio Oliveira	8826b1e680	brw: Use a more specific builder helper in combine constants ... Also remove commentary about older Gfx versions that don't apply anymore. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34681>	2025-07-19 17:49:47 +00:00
Caio Oliveira	ac2b072312	brw: Add more specific brw_builder helpers ... Replace uses of brw_builder::at() with various more descriptive variants. Use block pointer from instruction when possible. A couple of special cases remained and will be handled in separate patches. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34681>	2025-07-19 17:49:47 +00:00
Caio Oliveira	6c5132ec9a	brw: Move insert/remove code to the block ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34681>	2025-07-19 17:49:46 +00:00
Konstantin Seurer	d28ff8050a	radv/rt: Use inv_dir for software ray-triangle tests ... Reviewed-by: Natalie Vock <natalie.vock@gmx.de> Reviewed-by: Autumn Ashton <misyl@froggi.es> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36213>	2025-07-19 16:35:37 +00:00
Konstantin Seurer	5494789e89	radv/rt: Optimize emulated ray-triangle tests ... The imod instructions are lowered to 4 alu instructions each. We can do better by packing the results with the values for kz. Reviewed-by: Natalie Vock <natalie.vock@gmx.de> Reviewed-by: Autumn Ashton <misyl@froggi.es> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36213>	2025-07-19 16:35:37 +00:00
Konstantin Seurer	d140f2a6a2	radv: Implement watertightness for emulated RT ... Instead of using fp64 (Which is broken in some cases) the new approach only uses fp32 and implements tiebreaking for edge/vertex hits. Using fp32 is also much faster, improving performance of q2rtx by around 40%. Reviewed-by: Natalie Vock <natalie.vock@gmx.de> Reviewed-by: Autumn Ashton <misyl@froggi.es> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36213>	2025-07-19 16:35:36 +00:00
Konstantin Seurer	55641f9ca0	radv: Disable pointer flags and the GFX12 WA for emulated RT ... Reviewed-by: Natalie Vock <natalie.vock@gmx.de> Reviewed-by: Autumn Ashton <misyl@froggi.es> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36213>	2025-07-19 16:35:36 +00:00
Konstantin Seurer	df44b353ad	radv: Optimize ray tracing position fetch ... Gets rid of a lot of indirection when fetching triangle positions. Storing the primitive address increases register pressure by a bit but the traversal shader which should have the highest register demand should not be affected when position fetch is not used. Totals: Instrs: 4021686 -> 4022435 (+0.02%); split: -0.01%, +0.03% CodeSize: 21235812 -> 21235832 (+0.00%); split: -0.02%, +0.02% Latency: 23402275 -> 23412110 (+0.04%); split: -0.04%, +0.09% InvThroughput: 4352818 -> 4352206 (-0.01%); split: -0.04%, +0.02% VClause: 101906 -> 102058 (+0.15%); split: -0.03%, +0.18% Copies: 342210 -> 342368 (+0.05%); split: -0.09%, +0.14% Branches: 114988 -> 114993 (+0.00%) PreVGPRs: 26551 -> 27111 (+2.11%) VALU: 2249366 -> 2249524 (+0.01%); split: -0.01%, +0.02% SALU: 529828 -> 529808 (-0.00%); split: -0.01%, +0.00% Reviewed-by: Natalie Vock <natalie.vock@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35533>	2025-07-19 16:07:59 +00:00