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etnaviv: Update headers from rnndb
Update from rnndb commit 19bc9377a80a ("rnndb: rename
UNIFORM_CACHE to CONTROL and document code cache flushing")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36114>
This commit is contained in:
Lucas Stach
Marge Bot
parent
d59c22b6e1
commit
b093fa9dcf
2 changed files with 33 additions and 33 deletions
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- state_hi.xml ( 35909 bytes, from 2024-12-05 12:09:36)
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- copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03)
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- state_2d.xml ( 52271 bytes, from 2023-05-30 20:50:02)
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- state_3d.xml ( 89428 bytes, from 2025-03-14 21:09:00)
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- state_3d.xml ( 89609 bytes, from 2025-07-13 22:31:44)
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- state_blt.xml ( 14592 bytes, from 2024-12-05 12:09:36)
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- state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03)
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@ -257,18 +257,8 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_VS_RANGE_HIGH__SHIFT 16
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#define VIVS_VS_RANGE_HIGH(x) (((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK)
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#define VIVS_VS_UNIFORM_CACHE 0x00000860
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#define VIVS_VS_UNIFORM_CACHE_FLUSH 0x00000001
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#define VIVS_VS_UNIFORM_CACHE_PS 0x00000010
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#define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING 0x00001000
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#define VIVS_VS_UNIFORM_BASE 0x00000864
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#define VIVS_VS_ICACHE_CONTROL 0x00000868
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#define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001
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#define VIVS_VS_ICACHE_CONTROL_FLUSH_VS 0x00000010
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#define VIVS_VS_ICACHE_CONTROL_FLUSH_PS 0x00000020
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#define VIVS_VS_INST_ADDR 0x0000086c
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#define VIVS_VS_HALTI5_OUTPUT_COUNT 0x00000870
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@ -281,9 +271,7 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_VS_NEWRANGE_LOW 0x00000874
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#define VIVS_VS_HALTI5_UNK00878 0x00000878
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#define VIVS_VS_HALTI5_UNK00880 0x00000880
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#define VIVS_VS_NEWRANGE_HIGH 0x00000878
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#define VIVS_VS_HALTI1_UNK00884 0x00000884
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@ -317,7 +305,7 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_VS_HALTI5_UNK008B8 0x000008b8
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#define VIVS_VS_NEWRANGE_HIGH 0x000008bc
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#define VIVS_VS_HALTI5_RANGE_HIGH 0x000008bc
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#define VIVS_VS_HALTI5_INPUT(i0) (0x000008c0 + 0x4*(i0))
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#define VIVS_VS_HALTI5_INPUT__ESIZE 0x00000004
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@ -744,7 +732,9 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_PS_NEWRANGE_LOW 0x0000087c
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#define VIVS_PS_NEWRANGE_HIGH 0x00001090
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#define VIVS_PS_NEWRANGE_HIGH 0x00000880
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#define VIVS_PS_HALTI5_RANGE_HIGH 0x00001090
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#define VIVS_PS_ICACHE_COUNT 0x00001094
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@ -1976,6 +1966,16 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_SH 0x00000000
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#define VIVS_SH_CONTROL 0x00000860
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#define VIVS_SH_CONTROL_PS_CODE 0x00000001
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#define VIVS_SH_CONTROL_PS_UNIFORM 0x00000010
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#define VIVS_SH_CONTROL_RTNE_ROUNDING 0x00001000
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#define VIVS_SH_ICACHE_CONTROL 0x00000868
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#define VIVS_SH_ICACHE_CONTROL_ENABLE 0x00000001
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#define VIVS_SH_ICACHE_CONTROL_FLUSH_VS 0x00000010
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#define VIVS_SH_ICACHE_CONTROL_FLUSH_PS 0x00000020
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#define VIVS_SH_CONFIG 0x00015600
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#define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002
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#define VIVS_SH_CONFIG_DUAL16 0x00000004
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@ -652,20 +652,20 @@ etna_emit_state(struct etna_context *ctx)
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assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo);
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/* Set icache (VS) */
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etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0);
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etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
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etna_set_state(stream, VIVS_VS_HALTI5_RANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
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assert(ctx->shader_state.VS_INST_ADDR.bo);
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etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
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etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
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etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
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etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, VIVS_SH_ICACHE_CONTROL_ENABLE);
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etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1);
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/* Set icache (PS) */
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etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0);
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etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
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etna_set_state(stream, VIVS_PS_HALTI5_RANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
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assert(ctx->shader_state.PS_INST_ADDR.bo);
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etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
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etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
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etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
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etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, VIVS_SH_ICACHE_CONTROL_ENABLE);
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etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1);
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} else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) {
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@ -674,18 +674,18 @@ etna_emit_state(struct etna_context *ctx)
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/* Set icache (VS) */
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etna_set_state(stream, VIVS_VS_RANGE,
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VIVS_VS_RANGE_HIGH(ctx->shader_state.vs_inst_mem_size / 4 - 1));
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etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
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VIVS_VS_ICACHE_CONTROL_ENABLE |
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VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
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etna_set_state(stream, VIVS_SH_ICACHE_CONTROL,
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VIVS_SH_ICACHE_CONTROL_ENABLE |
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VIVS_SH_ICACHE_CONTROL_FLUSH_VS);
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assert(ctx->shader_state.VS_INST_ADDR.bo);
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etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
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/* Set icache (PS) */
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etna_set_state(stream, VIVS_PS_RANGE,
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VIVS_PS_RANGE_HIGH(ctx->shader_state.ps_inst_mem_size / 4 - 1));
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etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
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VIVS_VS_ICACHE_CONTROL_ENABLE |
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VIVS_VS_ICACHE_CONTROL_FLUSH_PS);
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etna_set_state(stream, VIVS_SH_ICACHE_CONTROL,
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VIVS_SH_ICACHE_CONTROL_ENABLE |
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VIVS_SH_ICACHE_CONTROL_FLUSH_PS);
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assert(ctx->shader_state.PS_INST_ADDR.bo);
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etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
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} else {
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@ -694,9 +694,9 @@ etna_emit_state(struct etna_context *ctx)
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/* Upload shader directly, first flushing and disabling icache if
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* supported on this hw */
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if (screen->specs.has_icache) {
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etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
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VIVS_VS_ICACHE_CONTROL_FLUSH_PS |
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VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
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etna_set_state(stream, VIVS_SH_ICACHE_CONTROL,
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VIVS_SH_ICACHE_CONTROL_FLUSH_PS |
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VIVS_SH_ICACHE_CONTROL_FLUSH_VS);
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}
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if (screen->specs.has_unified_instmem) {
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etna_set_state(stream, VIVS_VS_RANGE,
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@ -723,12 +723,12 @@ etna_emit_state(struct etna_context *ctx)
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}
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if (do_uniform_flush)
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etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
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etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE);
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etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
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if (do_uniform_flush)
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etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
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etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE | VIVS_SH_CONTROL_PS_UNIFORM);
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etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
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@ -741,14 +741,14 @@ etna_emit_state(struct etna_context *ctx)
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} else {
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/* ideally this cache would only be flushed if there are VS uniform changes */
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if (do_uniform_flush)
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etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
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etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE);
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if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
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etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
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/* ideally this cache would only be flushed if there are PS uniform changes */
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if (do_uniform_flush)
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etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
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etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE | VIVS_SH_CONTROL_PS_UNIFORM);
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if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
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etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
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