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nir: introduce "inexact associative" property
nothing currently uses the associative flag, but they will change soon. we need to stop incorrectly marking fmul/fadd/etc as associative, because they're not, but they almost are. distinguish these properties so we can correctly handle floating point rules without any opcode-based special casing. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36257>
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2 changed files with 12 additions and 4 deletions
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@ -1435,6 +1435,13 @@ typedef enum {
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* comparison.
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*/
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NIR_OP_IS_SELECTION = (1 << 2),
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/**
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* Operation is associative mathematically (as real numbers), but not
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* associative with floating-point math. This can be treated as associative
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* iff the operation's exact bit is not set.
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*/
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NIR_OP_IS_INEXACT_ASSOCIATIVE = (1 << 3),
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} nir_op_algebraic_property;
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/* vec16 is the widest ALU op in NIR, making the max number of input of ALU
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@ -149,6 +149,7 @@ def type_base_type(type_):
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# sources.
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_2src_commutative = "2src_commutative "
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associative = "associative "
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inexact_associative = "inexact_associative "
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selection = "selection "
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# global dictionary of opcodes
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@ -610,7 +611,7 @@ def binop_reduce_all_sizes(name, output_size, src_type, prereduce_expr,
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binop_reduce("b32" + name[1:], output_size, tbool32, src_type,
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prereduce_expr, reduce_expr, final_expr, description)
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binop("fadd", tfloat, _2src_commutative + associative,"""
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binop("fadd", tfloat, _2src_commutative + inexact_associative,"""
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if (nir_is_rounding_mode_rtz(execution_mode, bit_size)) {
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if (bit_size == 64)
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dst = _mesa_double_add_rtz(src0, src1);
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@ -652,7 +653,7 @@ binop_convert("uabs_isub", tuint, tint, "", """
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""")
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binop("uabs_usub", tuint, "", "(src1 > src0) ? (src1 - src0) : (src0 - src1)")
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binop("fmul", tfloat, _2src_commutative + associative, """
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binop("fmul", tfloat, _2src_commutative + inexact_associative, """
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if (nir_is_rounding_mode_rtz(execution_mode, bit_size)) {
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if (bit_size == 64)
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dst = _mesa_double_mul_rtz(src0, src1);
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@ -663,7 +664,7 @@ if (nir_is_rounding_mode_rtz(execution_mode, bit_size)) {
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}
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""")
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binop("fmulz", tfloat32, _2src_commutative + associative, """
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binop("fmulz", tfloat32, _2src_commutative + inexact_associative, """
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if (src0 == 0.0 || src1 == 0.0)
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dst = 0.0;
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else if (nir_is_rounding_mode_rtz(execution_mode, 32))
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@ -1755,7 +1756,7 @@ opcode("udot_2x16_uadd_sat", 0, tint32, [0, 0, 0], [tuint32, tuint32, tint32],
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unop_numeric_convert("bf2f", tfloat32, tuint16, "_mesa_bfloat16_bits_to_float(src0)")
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unop_numeric_convert("f2bf", tuint16, tfloat32, "_mesa_float_to_bfloat16_bits_rte(src0)")
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binop("bfmul", tuint16, _2src_commutative + associative, """
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binop("bfmul", tuint16, _2src_commutative + inexact_associative, """
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const float a = _mesa_bfloat16_bits_to_float(src0);
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const float b = _mesa_bfloat16_bits_to_float(src1);
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dst = _mesa_float_to_bfloat16_bits_rte(a * b);
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