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Author SHA1 Message Date
Rob Clark
dc00ec154b freedreno: better manage our WFI's 
Updates to non-banked registers, CP_LOAD_STATE, etc, need a WFI if there
is potentially pending rendering.  Track this better, and add fd_wfi()
calls everywhere that might potentially need CP_WAIT_FOR_IDLE.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 12:10:17 -05:00
Rob Clark
1fe9df8f29 freedreno/a3xx: add logicop 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:59:25 -05:00
Rob Clark
8d27be2633 freedreno/a3xx: handle frag z write 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:58:47 -05:00
Rob Clark
083b27a1b1 freedreno: resync generated headers 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:57:39 -05:00
Rob Clark
98c1111462 freedreno/a3xx: fix const confusion 
Gallium can leave const buffers bound above what is used by the current
shader.  Which can have a couple bad effects:

1) write beyond const space assigned, which can trigger HLSQ lockup
2) double emit of immed consts, first with bound const buffer vals
followed by with actual immed vals.  This seems to be a sort of
undefined condition.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:57:09 -05:00
Rob Clark
5c6961efae freedreno/a3xx/compiler: compiler cleanups 
Drop color/pos/psize_regid, plus a few compiler and IR cleanups.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:53:21 -05:00
Rob Clark
69eca28dd0 freedreno/compiler/a3xx: remove lowered instructions 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:52:27 -05:00
Rob Clark
0f2df4ff90 freedreno: add tgsi lowering pass 
Currently lowers the following instructions:

   DST, XPD, SCS, LRP, FRC, POW, LIT, EXP, LOG, DP4,
   DP3, DPH, DP2

translating these into equivalent simpler TGSI instructions.

This probably should be moved to util so other drivers can use
it, but just adding under freedreno for now so that I can clear
out a lot of the lowering code in a3xx compiler before beginning
to add new compiler.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:50:10 -05:00
Rob Clark
7524756199 freedreno/a3xx/compiler: add CLAMP 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:49:31 -05:00
Rob Clark
fafe16a8a0 freedreno/a3xx/compiler: various fixes 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:49:06 -05:00
Rob Clark
4971628bae freedreno: ctx should hold ref to dev 
The ctx should hold ref to dev to avoid problems if screen is destroyed
before ctx.  Doesn't really fix the egl/glx issues, but at least it
prevents things from getting much worse.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:47:08 -05:00
Rob Clark
303df12db8 freedreno: add prims-emitted driver query 
Signed-off-by: Rob Clark <robclark@freedesktop.org>
 2014-02-01 11:45:19 -05:00
Roland Scheidegger
1d53603f1f llvmpipe: fix denorm handling for r11g11b10_float format when blending 
The code re-enabling denorms for small float formats did not recognize
this format due to format handling hacks (mainly, the lp_type doesn't have
the floating bit set).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
 2014-01-31 19:51:06 +01:00
Siavash Eliasi
03065ea05c r600g: Removed unnecessary positivity check for unsigned int variable. 
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-31 00:50:08 +01:00
Ian Romanick
25c14f40f3 freedreno: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64 
Allocations actually have page alignment, but 64 is still a reasonable
value.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
 2014-01-29 09:11:39 -07:00
Siavash Eliasi
205e624048 ilo: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64 
Ian manually ran the map_buffer_range* tests and the
arb_map_buffer_alignment-* tests, but he did not do a full piglit run.

v2 (idr): Use 64 instead of 4096

Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
 2014-01-29 09:11:39 -07:00
Siavash Eliasi
75081391a4 svga: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64 
v2: Fixed setting switch cases prior to
PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT incorrectly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
 2014-01-29 09:11:39 -07:00
Siavash Eliasi
d273fe72df i915g: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64 
v2: Fixed setting switch cases prior to
PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT incorrectly.
 2014-01-29 09:11:39 -07:00
Siavash Eliasi
4329e99b23 i915g: Use alignment of 64 instead of 16 for buffer allocation 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
 2014-01-29 09:09:41 -07:00
Siavash Eliasi
809d3a7d25 llvmpipe: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64 
v2: Fixed setting switch cases prior to
PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT incorrectly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
 2014-01-29 09:09:41 -07:00
Siavash Eliasi
6317664de0 llvmpipe: Use alignment of 64 instead of 16 for buffer allocation 
v2: Changed allocation alignment of llvmpipe_displaytarget_layout.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
 2014-01-29 09:09:41 -07:00
Siavash Eliasi
c83b34c43b softpipe: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64 
v2: Fixed setting switch cases prior to
PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT incorrectly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
 2014-01-29 09:09:41 -07:00
Siavash Eliasi
e36759a81e softpipe: Use alignment of 64 instead of 16 for buffer allocation 
v2: Changed allocation alignment in softpipe_displaytarget_layout.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
 2014-01-29 09:09:41 -07:00
Stéphane Marchesin
023a50dd9b i915g: support more PIPE_CAPs 2014-01-28 18:56:54 -08:00
Michel Dänzer
f8e16010e5 radeonsi: Put GS ring buffer descriptors with streamout buffer descriptors 
And mark the constant buffers as read only for the GPU again.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:09:26 +09:00
Michel Dänzer
d7c68e2dc1 radeonsi: Enable OpenGL 3.3 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:09:14 +09:00
Michel Dänzer
db9d6af862 radeonsi: Geometry shader micro-optimizations 
Move parameter loads out of loops, and use the instruction offset
instead of a VGPR for the vertex attribute offset when writing to the
ESGS ring buffer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:09:04 +09:00
Michel Dänzer
3b3687adcb radeonsi: We don't support indirect addressing of geometry shader inputs 
Fixes piglit spec/glsl-1.50/execution/geometry/dynamic_input_array_index

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:54 +09:00
Michel Dänzer
b4e14931a9 radeonsi: Pass VS resource descriptors to the HW ES shader stage as well 
This makes sure constants and samplers work in the vertex shader even
when a geometry shader is active.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:43 +09:00
Michel Dänzer
67e385b3b7 radeonsi: Fix streamout from geometry shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:33 +09:00
Michel Dänzer
d88a375229 radeonsi: Simplify shader PM4 state handling 
Just always bind the current states before drawing.

Besides the simplification, as a bonus this makes sure the VS hardware
shader stage always uses the GS copy shader when a geometry shader is
active, fixing a number of GS related piglit tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:21 +09:00
Michel Dänzer
e884c560a6 radeonsi: Properly match ES outputs to GS inputs 
Fixes piglit vs-gs-arrays-within-blocks-pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:10 +09:00
Michel Dänzer
e1df0d45c4 radeonsi: Really dump TGSI code before any TGSI->LLVM conversion attempt 
While we're at it, use the local variable 'sel'.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:58 +09:00
Michel Dänzer
7b19c391f4 radeonsi: Also export clip distances with geometry shader 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:48 +09:00
Michel Dänzer
8afde9fa23 radeonsi: Take GS into account for VS state in more places 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:35 +09:00
Michel Dänzer
28630713b2 radeonsi: Handle adjacency primitives 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:23 +09:00
Michel Dänzer
d8b3d806fc radeonsi: Handle TGSI_SEMANTIC_PRIMID 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:11 +09:00
Michel Dänzer
7c7d7380f1 radeonsi: Generalize counting of shader parameters 
Now it covers ES->GS as well as VS->PS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:06:58 +09:00
Michel Dänzer
f07a96dad1 radeonsi: Fix handling of geometry shader output vertex ID 
It needs to increment at shader runtime, not at shader compile time, as
the geometry shader can emit vertices in loops. LLVM automagically
converts the ID back to an immediate value if its value can be
determined at compile time.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:06:45 +09:00
Michel Dänzer
404b29d765 radeonsi: Initial geometry shader support 
Partly based on the corresponding r600g work by Vadim Girlin and Dave
Airlie.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:06:28 +09:00
Michel Dänzer
51f89a03e1 radeonsi: Refactor shader input / output handling code 
In preparation for adding geometry shader support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:05:58 +09:00
Tom Stellard
7b4592a489 r600g,radeonsi: Don't set resource_create in r600_common_screen_init() 
r600g and radeonsi have different implementations of resource_create.

https://bugs.freedesktop.org/show_bug.cgi?id=74139

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-28 07:24:11 -08:00
Michel Dänzer
a818bf481a r600g: s/r600_llvm_gpu_string/r600_get_llvm_processor_name/ 
Fixes build failure introduced by commit
65dc588bfd ('r600g,radeonsi: consolidate
get_compute_param'), which consolidated the former into the latter.
 2014-01-28 10:12:32 +09:00
Marek Olšák
7209703432 radeonsi: cleanup includes, add missing license 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:40:13 +01:00
Marek Olšák
2942124db8 radeonsi: remove open-coded PS_PARTIAL_FLUSH event 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:40:10 +01:00
Marek Olšák
8a4d7c296f radeonsi: move some inline functions from si_pipe.h to si_state.c 
And si_tex_aniso_filter is unused.

v2: remove INLINE occurences

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:40:05 +01:00
Marek Olšák
530348680a radeonsi: remove si_resource.h 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:40:04 +01:00
Marek Olšák
6e38a3de8a radeonsi: remove si.h 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:40:02 +01:00
Marek Olšák
27a73a1b94 radeonsi: move si_upload_const_buffer to a better place 
This gets rid of another file.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:59 +01:00
Marek Olšák
9f5c037ab9 radeonsi: inline si_translate_index_buffer 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:57 +01:00