Commit graph

11465 commits

Author SHA1 Message Date
Ilia Mirkin
f76c7ad5b1 nv50: only over-allocate by a page for code
The pre-fetching doesn't go too far. Tested with over-allocating by only
a page, and didn't see any errors in dmesg. Saves ~512KB of VRAM.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 10.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>
2014-02-06 18:50:19 -05:00
Ilia Mirkin
364bdd2419 nv50: fix layerid to be the fp input number rather than vp output number
In the tests they were the same so it didn't matter, but indications are
that this is the correct behaviour. Also take this opportunity to
(trivially) support using gl_Layer in fp.

Cc: 10.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>
2014-02-06 18:03:24 -05:00
Ilia Mirkin
c7373b7dc7 nv50: rework primid logic
Functionally identical but much simpler. Should also better integrate
with future layer/viewport changes/fixes.

Cc: 10.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>
2014-02-06 18:02:57 -05:00
Marek Olšák
559af1df10 gallium/radeon: fix warnings 2014-02-06 17:43:29 +01:00
Marek Olšák
c32114460d gallium: remove PIPE_USAGE_STATIC
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-02-06 17:37:34 +01:00
Marek Olšák
2be5bbdd97 r600g,radeonsi: set resource domains in one place (v2)
v2: This doesn't change the behavior. It only moves the tiling check
    to r600_init_resource and removes the usage parameter.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-02-06 17:29:59 +01:00
Christian König
96e8b916a7 radeon: just don't map VRAM buffers at all
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-02-06 16:08:22 +01:00
Christian König
9b218dcdd7 radeon/video: directly create buffers in the right domain
Avoid moving things around on start of stream.

Signed-off-by: Christian König <christian.koenig@amd.com>
2014-02-06 15:54:14 +01:00
Christian König
7bcfb0bc8f radeon/video: seperate common video functions
Signed-off-by: Christian König <christian.koenig@amd.com>
2014-02-06 15:54:13 +01:00
Dave Airlie
79ea0f4506 r600g: add support for geom shaders to r600/r700 chipsets (v2)
This is my first attempt at enabling r600/r700 geometry shaders,
the basic tests pass on both my rv770 and my rv635,

It requires this kernel patch:
http://www.spinics.net/lists/dri-devel/msg52745.html

v2: address Alex comments.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:43 +10:00
Dave Airlie
ccea799ee3 r600g: enable GLSL 3.30 on evergreen GPUs
This throws the switch to enable GL 3.3 and GLSL 330.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:43 +10:00
Dave Airlie
c6cfc54db0 r600g: properly propogate clip dist write value
This moves the value from the GS shader to the copy shader so the registers
are setup correctly.

fixes tests/spec/glsl-1.50/execution/geometry/clip-distance-out-values.shader_test

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:43 +10:00
Dave Airlie
b209afb153 r600g: calculate a better value for array_size (v2)
attempt to calculate a better value for array size to avoid breaking apps.

v2: use 0xfff like streamout, suggested by Grigori

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:42 +10:00
Dave Airlie
ce9e939144 r600g: fix CAYMAN geometry shader support
cayman has a different end of program bit, so do that properly.

fixes hangs with geom shader tests on cayman.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:42 +10:00
Dave Airlie
7ec5e883f2 r600g: fix up shader out misc stuff for copy shader
set the correct values so the misc out register is setup correctly
for the copy shader.

This also updates the state for the gs copy shader so the hw
gets programmed correctly.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:42 +10:00
Dave Airlie
7863611de3 r600g: port the layered surface rendering patch from radeonsi
This just makes r600 and evergreen do what the radeonsi codepaths do
for layered rendering. This makes the 2d amd_vertex_shader_layer test
pass on evergreen.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:41 +10:00
Dave Airlie
f89394be98 r600g: initial VS output layer support
This just adds support for emitting the proper value in the VS out misc.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:41 +10:00
Dave Airlie
5191937352 r600g: setup const texture buffers for geom shaders
This just enables the workarounds we have for vertex/pixel shaders
for geom shaders as well.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:41 +10:00
Dave Airlie
afce47fb0b r600g: calculate correct cut value
This selects the cut value depending on the shader selected.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:41 +10:00
Dave Airlie
0d79d5da40 r600g: fix dynamic_input_array_index.shader_test
This follows what fglrx does, it unpacks the input we are
going to indirect into a bunch of registers and indirects
inside them.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:40 +10:00
Dave Airlie
e12147e9f6 r600g: add support for indirect geom ring writes
We need to be able to write to the ring using a base register
for when we emit vertices in a loop, in theory the SB compiler
could collapse these indirect writes to direct writes if the
register value is constant and known, but that is outside my
pay grade.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:40 +10:00
Dave Airlie
cda63db780 r600g: write proper output prim type
Vadim's code derived it from the info.mode, but it needs
to be takes from the geometry shader output primitive.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:40 +10:00
Dave Airlie
2b0be2015d r600g: enable instance cnt register with new enough kernel
The instance cnt register was missing for a few kernels,
with a new enough kernel we can output it.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:39 +10:00
Dave Airlie
f4652babbd r600g: add primitive input support for gs
only enable prim id if gs uses it

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:39 +10:00
Dave Airlie
b0e842bd9f r600g: emit streamout from dma copy shader
This enables streamout with GS in the mix, from the
VS dma shader.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:39 +10:00
Dave Airlie
20adc7449c r600g/gs: fix cases where number of gs inputs != number of gs outputs
this fixes a bunch of the geom shader built-in tests

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:39 +10:00
Dave Airlie
defebc0293 r600g: increase array base for exported parameters
Trivial fix to Vadim's code.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:38 +10:00
Dave Airlie
d9954e402f r600g: initialise the geom shader loop registers.
As we do for vertex and pixel shaders.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:38 +10:00
Dave Airlie
461c463bb2 r600g: emit NOPs at end of shaders in more cases
If the shader has no CF clauses at all emit an nop
If the last instruction is an ENDLOOP add a NOP for the LOOP to go to
if the last instruction is CALL_FS add a NOP

These fix a bunch of hangs in the geometry shader tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:38 +10:00
Dave Airlie
c4782a58c3 r600g: don't enable SB for geom shaders
SB needs fixes for three GS instructions it seems to raise
them outside loops etc despite my best efforts.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:37 +10:00
Dave Airlie
5758a76d04 r600g/sb: add MEM_RING support
Although we don't use SB on geom shaders, the VS copy shader will use it
so we might as well implement MEM_RING support in sb.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:37 +10:00
Dave Airlie
eeead9b8ed r600g: don't fail if we can't map VS->GS ring entries
This can happen in normal operation, so don't report an error on it,
just continue.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:37 +10:00
Vadim Girlin
1371d65a7f r600g: initial support for geometry shaders on evergreen (v2)
This is Vadim's initial work with a few regression fixes squashed in.

v2: (airlied)
fix regression in glsl-max-varyings - need to use vs and ps_dirty
fix regression in shader exports from rebasing.
whitespace fixing.
v2.1: squash fix assert

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:49:11 +10:00
Vadim Girlin
34ee1d0f9f r600g: add hw register definitions for GS block setup
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:40:42 +10:00
Vadim Girlin
a144bc29b5 r600g: defer shader variant selection and depending state updates
[airlied: fix dropped streamout line - fix for master]

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:40:38 +10:00
Dave Airlie
ae29a098ea r600g/bc: add support for indexed memory writes.
It looks like we need these for geom shaders in the future.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-05 10:40:33 +10:00
Vadim Girlin
552aae7e47 r600g: move barrier and end_of_program bits from output to cf struct (v2)
v2: fix regression on r600 NOP instructions.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-02-05 10:40:23 +10:00
Dave Airlie
29a43cb0b6 r600g: split streamout emit code into a separate function
For geometry shaders we need to call this code from a second place.

Just move it out for now to keep future patches cleaner.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-02-05 10:40:17 +10:00
Marek Olšák
07075cf350 r600g,radeonsi: skip unnecessary buffer_is_busy call, add a comment 2014-02-04 20:19:16 +01:00
Marek Olšák
08f0344cf3 r600g,radeonsi: skip busy-checking for DISCARD_RANGE if it has been done already 2014-02-04 20:19:16 +01:00
Marek Olšák
796e2fba8c r600g,radeonsi: treat DYNAMIC and STREAM usage as STAGING 2014-02-04 20:19:16 +01:00
Marek Olšák
0354b769c2 gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERS
This can be derived from the shader caps.

All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots
for each shader stage.
2014-02-04 20:19:16 +01:00
Christian König
c3c24c3acc radeon/uvd: fix feedback buffer handling v2
Without the correct feedback buffer size UVD runs
into an error on each frame, reducing the maximum FPS.

v2: fixing Michels comments

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: "10.1" "10.0" "9.2" <mesa-stable@lists.freedesktop.org>
2014-02-04 13:10:50 +01:00
Rob Clark
1b886078db freedreno: enabling binning and opt by default
Hw binning pass doesn't seem to have broken anything.  And optimizing
compiler fixes a lot of shaders and doesn't seem to break anything.  So
re-org slightly FD_MESA_DEBUG params and make both hw binning and
optimizer enabled by default.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-03 18:26:53 -05:00
Rob Clark
554f1ac00c freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.

The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions.  The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).

The register assignment is currently split out as a standalone pass.  I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).

There are a couple new debug options for FD_MESA_DEBUG env var:

  optmsgs - enable debug prints in optimizer
  optdump - dump instruction graph in .dot format, for example:

http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot

At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1].  So even though it
is not finished, it seems useful to merge it in it's current state.

[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):

163b6306b1

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-03 18:26:53 -05:00
Rob Clark
f0e2d7ab46 freedreno/a3xx/compiler: split out old compiler
For the time being, keep old compiler as fallback for things that the
new compiler does not support yet.  Split out as it's own commit to make
the later new-compiler commits easier to follow.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-03 18:26:53 -05:00
Rob Clark
a418573c4d freedreno/a3xx/compiler: prepare for new compiler
Shuffle things around to prepare for new compiler.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-03 18:26:53 -05:00
Rob Clark
f08d2b1c0f freedreno/a3xx: remove useless reg tracking in disasm-a3xx
Not really used for anything anymore.  So strip it out and avoid
conflicting symbols with upcoming new-compiler.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-03 18:26:53 -05:00
Brian Paul
97fdace6d7 svga: check shader size against max command buffer size
If the shader is too large, plug in a dummy shader.  This patch also
reworks the existing dummy shader code.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-02-03 12:40:13 -07:00
Brian Paul
4686f610b1 svga: refactor some shader code
Put common code in new svga_shader.c file.  Considate separate vertex/
fragment shader ID generation.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-02-03 12:40:13 -07:00