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synced 2026-05-08 22:08:26 +02:00
r600g: split streamout emit code into a separate function
For geometry shaders we need to call this code from a second place. Just move it out for now to keep future patches cleaner. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
07075cf350
commit
29a43cb0b6
1 changed files with 110 additions and 103 deletions
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@ -875,6 +875,114 @@ static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
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return 0;
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}
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static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so)
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{
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unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
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int i, j, r;
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/* Sanity checking. */
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if (so->num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
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R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
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r = -EINVAL;
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goto out_err;
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}
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for (i = 0; i < so->num_outputs; i++) {
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if (so->output[i].output_buffer >= 4) {
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R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
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so->output[i].output_buffer);
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r = -EINVAL;
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goto out_err;
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}
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}
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/* Initialize locations where the outputs are stored. */
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for (i = 0; i < so->num_outputs; i++) {
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so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
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/* Lower outputs with dst_offset < start_component.
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*
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* We can only output 4D vectors with a write mask, e.g. we can
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* only output the W component at offset 3, etc. If we want
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* to store Y, Z, or W at buffer offset 0, we need to use MOV
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* to move it to X and output X. */
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if (so->output[i].dst_offset < so->output[i].start_component) {
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unsigned tmp = r600_get_temp(ctx);
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for (j = 0; j < so->output[i].num_components; j++) {
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struct r600_bytecode_alu alu;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.src[0].sel = so_gpr[i];
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alu.src[0].chan = so->output[i].start_component + j;
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alu.dst.sel = tmp;
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alu.dst.chan = j;
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alu.dst.write = 1;
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if (j == so->output[i].num_components - 1)
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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so->output[i].start_component = 0;
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so_gpr[i] = tmp;
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}
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}
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/* Write outputs to buffers. */
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for (i = 0; i < so->num_outputs; i++) {
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struct r600_bytecode_output output;
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memset(&output, 0, sizeof(struct r600_bytecode_output));
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output.gpr = so_gpr[i];
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output.elem_size = so->output[i].num_components;
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output.array_base = so->output[i].dst_offset - so->output[i].start_component;
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output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
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output.burst_count = 1;
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output.barrier = 1;
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/* array_size is an upper limit for the burst_count
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* with MEM_STREAM instructions */
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output.array_size = 0xFFF;
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output.comp_mask = ((1 << so->output[i].num_components) - 1) << so->output[i].start_component;
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if (ctx->bc->chip_class >= EVERGREEN) {
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switch (so->output[i].output_buffer) {
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case 0:
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output.op = CF_OP_MEM_STREAM0_BUF0;
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break;
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case 1:
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output.op = CF_OP_MEM_STREAM0_BUF1;
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break;
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case 2:
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output.op = CF_OP_MEM_STREAM0_BUF2;
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break;
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case 3:
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output.op = CF_OP_MEM_STREAM0_BUF3;
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break;
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}
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} else {
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switch (so->output[i].output_buffer) {
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case 0:
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output.op = CF_OP_MEM_STREAM0;
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break;
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case 1:
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output.op = CF_OP_MEM_STREAM1;
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break;
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case 2:
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output.op = CF_OP_MEM_STREAM2;
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break;
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case 3:
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output.op = CF_OP_MEM_STREAM3;
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break;
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}
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}
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r = r600_bytecode_add_output(ctx->bc, &output);
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if (r)
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goto out_err;
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}
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return 0;
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out_err:
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return r;
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}
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static int r600_shader_from_tgsi(struct r600_screen *rscreen,
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struct r600_pipe_shader *pipeshader,
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@ -1263,109 +1371,8 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
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}
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/* Add stream outputs. */
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if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
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unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
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/* Sanity checking. */
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if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
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R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
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r = -EINVAL;
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goto out_err;
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}
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for (i = 0; i < so.num_outputs; i++) {
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if (so.output[i].output_buffer >= 4) {
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R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
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so.output[i].output_buffer);
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r = -EINVAL;
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goto out_err;
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}
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}
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/* Initialize locations where the outputs are stored. */
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for (i = 0; i < so.num_outputs; i++) {
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so_gpr[i] = shader->output[so.output[i].register_index].gpr;
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/* Lower outputs with dst_offset < start_component.
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*
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* We can only output 4D vectors with a write mask, e.g. we can
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* only output the W component at offset 3, etc. If we want
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* to store Y, Z, or W at buffer offset 0, we need to use MOV
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* to move it to X and output X. */
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if (so.output[i].dst_offset < so.output[i].start_component) {
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unsigned tmp = r600_get_temp(&ctx);
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for (j = 0; j < so.output[i].num_components; j++) {
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struct r600_bytecode_alu alu;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.src[0].sel = so_gpr[i];
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alu.src[0].chan = so.output[i].start_component + j;
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alu.dst.sel = tmp;
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alu.dst.chan = j;
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alu.dst.write = 1;
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if (j == so.output[i].num_components - 1)
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx.bc, &alu);
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if (r)
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return r;
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}
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so.output[i].start_component = 0;
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so_gpr[i] = tmp;
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}
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}
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/* Write outputs to buffers. */
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for (i = 0; i < so.num_outputs; i++) {
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struct r600_bytecode_output output;
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memset(&output, 0, sizeof(struct r600_bytecode_output));
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output.gpr = so_gpr[i];
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output.elem_size = so.output[i].num_components;
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output.array_base = so.output[i].dst_offset - so.output[i].start_component;
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output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
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output.burst_count = 1;
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output.barrier = 1;
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/* array_size is an upper limit for the burst_count
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* with MEM_STREAM instructions */
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output.array_size = 0xFFF;
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output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
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if (ctx.bc->chip_class >= EVERGREEN) {
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switch (so.output[i].output_buffer) {
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case 0:
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output.op = CF_OP_MEM_STREAM0_BUF0;
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break;
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case 1:
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output.op = CF_OP_MEM_STREAM0_BUF1;
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break;
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case 2:
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output.op = CF_OP_MEM_STREAM0_BUF2;
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break;
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case 3:
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output.op = CF_OP_MEM_STREAM0_BUF3;
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break;
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}
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} else {
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switch (so.output[i].output_buffer) {
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case 0:
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output.op = CF_OP_MEM_STREAM0;
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break;
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case 1:
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output.op = CF_OP_MEM_STREAM1;
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break;
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case 2:
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output.op = CF_OP_MEM_STREAM2;
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break;
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case 3:
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output.op = CF_OP_MEM_STREAM3;
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break;
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}
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}
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r = r600_bytecode_add_output(ctx.bc, &output);
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if (r)
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goto out_err;
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}
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}
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if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm)
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emit_streamout(&ctx, &so);
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/* export output */
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for (i = 0, j = 0; i < noutput; i++, j++) {
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