Commit graph

11465 commits

Author SHA1 Message Date
Roland Scheidegger
80e2cc0f97 llvmpipe: disable simple_shader optimization
This optimization disabled mask checks if the shader is simple enough.
While this should work correctly, the problem is that it can hide real issues
because shaders in practice are usually complex enough (8 instructions or 1
texture is already enough) so this doesn't get used, whereas dumbed-down
tests which should hit all the same code paths suddenly do something quite
different. This was the reason that bug 41787 could not be easily tracked as
stencil test not working correctly (piglit would in fact have failed some
tests without that optimization).
So disable it for now, it's unclear if it's much of a win in any case.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
e108716429 llvmpipe: fix early depth test / late depth write stencil issues
We actually did early depth/stencil test and late depth/stencil write even
when the shader could kill the fragment (alpha test or discard). Since it
matters for the new stencil value if the fragment is killed by depth/stencil
test or by the shader (in which case it will not reach the depth/stencil
test) this simply cannot work (we also would possibly skip writing the new
stencil value due to mask checks but this is a secondary issue).
So use late depth test / late depth write instead in this case.
(No piglit changes as it doesn't seem to hit such bogus early depth test
/ late depth write path.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
82d7733b52 llvmpipe: fix issue with not writing new stencil values
We did mask checks between depth/stencil testing and depth/stencil write.
This meant that if the depth/stencil test killed off all fragments we never
actually wrote the new stencil value. This issue affected all early/late
test/write combinations.
So move the mask check after depth/stencil write (for early depth test,
could do the same for late depth test but might not be worth it at that
point so just skip it there).
This addresses https://bugs.freedesktop.org/show_bug.cgi?id=41787.
Piglit does not hit this issue because of the simple_shader optimization
in generate_fs_loop() which means we're skipping the mask checks.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
3c91ef0f29 llvmpipe: (trivial) remove confusing code in stencil test
This was meant to disable some code which isn't needed when depth/stencil
isn't written. However, there's more code which wouldn't be needed in that
case so having the condition there was just odd (llvm will drop all the code
anyway).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
5314f5d829 llvmpipe: fix bug in early depth test / late depth write handling
Using wrong type if the format was less than 32bits.
No piglit changes as it doesn't hit that path.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Chia-I Wu
ff68f61bed ilo: set more fields of 3DSTATE_DEPTH_BUFFER
Set lod/layer related fields of 3DSTATE_DEPTH_BUFFER.  Since we always point
to a single level/layer, those fields are always zero and this commit
effectively makes no change.

While at it, make it easier to disable manual slice offset calculation.
2013-05-22 20:25:57 +08:00
Chia-I Wu
f3da711bea ilo: correctly set view extent in SURFACE_STATE
The view extent was set to be the same as the depth while it should be set to
the number of layers.  It makes a difference for 3D textures.

Also use this as a chance to clean up the code.
2013-05-22 18:12:01 +08:00
Chia-I Wu
bbb30398e5 ilo: avoid unnecessary emission of SO states
No need to emit 3DSTATE_SO_BUFFER and 3DSTATE_SO_DECL_LIST when SO is
disabled.  As the implicit flush done by the commands is also gone, emit an
explicit flush.
2013-05-22 18:09:17 +08:00
Michel Dänzer
d42a2df19c radeonsi: Fix user clip planes
4 more little piglits.

NOTE: This is a candidate for the 9.1 branch.
2013-05-21 17:50:13 +02:00
Michel Dänzer
e3befbca5e radeonsi: Handle TGSI_SEMANTIC_CLIPVERTEX
17 more little piglits.

NOTE: This is a candidate for the 9.1 branch.
2013-05-21 17:50:13 +02:00
Michel Dänzer
eb19163a4d radeonsi: Initial support for multiple constant buffers
Just enough to support an additional internal constant buffer for the user
clip planes.

NOTE: This is a candidate for the 9.1 branch.
2013-05-21 17:50:12 +02:00
Michel Dänzer
4730dea5f5 radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE
Two more little piglits.

NOTE: This is a candidate for the 9.1 branch.
2013-05-21 17:50:12 +02:00
Marek Olšák
2eac0aa1d8 radeonsi: increase array size for shader inputs and outputs
and add assertions to prevent buffer overflow. This fixes corruption
of the si_shader struct.

NOTE: This is a candidate for the 9.1 branch.

[ Cherry-pick of r600g commit da33f9b919 ]

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2013-05-21 17:47:44 +02:00
Chia-I Wu
2b7463cf3a ilo: use BLT engine to copy between textures
Emit XY_SRC_COPY_BLT to do the job.  Since ETC1 textures cannot be mapped for
reading, as is required by util_copy_resource_region, this fixes copying of
ETC1 textures.
2013-05-21 12:02:55 +08:00
Chia-I Wu
c44ebb4ef4 ilo: use BLT engine to copy between buffers
Emit (possibly multiple) SRC_COPY_BLT to copy between buffers of arbitrary
sizes.
2013-05-21 11:47:20 +08:00
Chia-I Wu
731cafe7b2 ilo: refactor blitter_xy_color_blt()
Add gen6_XY_COLOR_BLT() and let blitter_xy_color_blt() call the function.  Not
sure if this path is still being hit by any application.
2013-05-21 11:47:20 +08:00
Chia-I Wu
0d42a9e941 ilo: replace cp hooks by cp owner and flush callback
The problem with cp hooks is that when we switch from 3D ring to 2D ring, and
when there are active queries, we will emit 3D commands to 2D ring because
the new-batch hook is called.

This commit introduces the idea of cp owner.  When the cp is flushed, or when
another owner takes place, the current owner is notified, giving it a chance
to emit whatever commands there need to be.  With this mechanism, we can
resume queries when the 3D pipeline owns the cp, and pause queries when it
loses the cp.  Ring switch will just work.

As we still need to know when the cp bo is reallocated, a flush callback is
added.
2013-05-21 11:47:20 +08:00
Chia-I Wu
a04d8574c6 ilo: harware contexts are only for the render ring
The hardware context should not be passed for bo execution when the ring is
not the render ring.  Rename hw_ctx to render_ctx for clarity.
2013-05-21 11:47:19 +08:00
Chia-I Wu
1ed7b825cf ilo: update format mappings
Add more PIPE_FORMAT -> BRW_SURFACEFORMAT mappings, and update
surface_format_info from i965.
2013-05-21 11:47:19 +08:00
Chia-I Wu
bd8090a5af ilo: update headers from i965
Mainly for MI_LOAD_REGISTER_IMM and BCS_SWCTRL.
2013-05-21 11:47:19 +08:00
Vincent Lejeune
9fd7ea786c r600g/llvm: fix cubemap lod/bias 2013-05-20 20:23:19 +02:00
Vincent Lejeune
9a95fb1605 r600g/llvm: Fix texelFetchOffset-2D 2013-05-20 20:23:14 +02:00
Vincent Lejeune
32c9cbb38f r600g/llvm: Fix cubearray textureSize 2013-05-20 20:23:09 +02:00
Vincent Lejeune
9c2943601e r600g/llvm: Factorize code loading from const buffer. 2013-05-20 20:23:04 +02:00
Roland Scheidegger
f6beb4c6b6 llvmpipe: enable z32s8x24 format
Now that we can handle it both for sampling and as depth/stencil enable it.
Passes nearly all additional piglit tests which are now performed, with two
exceptions (one being a framebuffer blit which fails for all other formats
including stencil too as we don't support stencil blits, the other reporting
a unexpected GL error so doesn't look to be llvmpipe's fault).
2013-05-18 00:32:45 +02:00
Roland Scheidegger
070a9afb54 llvmpipe: handle z32s8x24 depth/stencil format
We need to split up the depth and stencil values in this case, and there's
some new logic required to handle float depth and stencil simultaneously.
Also make sure we get the 64bit zs clear values and masks propagated
correctly.
2013-05-18 00:32:33 +02:00
Roland Scheidegger
f3ad716e8f llvmpipe: get rid of unused tiled/linear logic
We do rendering to linear color buffers for quite some time, and since
switching to linear depth buffers all the tiled/linear logic was unused.
So get rid of (most) of it - there's still some LAYOUT_NONE things and
late allocation of resources which probably could be simplified.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-18 00:32:27 +02:00
Roland Scheidegger
87978518e9 llvmpipe: fix bogus handling of first_layer when setting up texture sampling
The code avoided first_layer parameter in the sampler interface (and needing
to do another calculation at runtime) by fixing up the base texture pointer
instead. Unfortunately, this didn't actually work as we have mip-first
texture layout so fixing up the base ptr by a fixed amount is very wrong if
there are mipmaps present. The wrong offsets caused misrendering and crashes.
Fix this by just adjusting the individual mip level offsets instead.
Spotted by Jose.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-18 00:32:18 +02:00
José Fonseca
6166ffeaf7 gallivm: Eliminate 8.8 fixed point intermediates from AoS sampling path.
This change was meant as a stepping stone to use PMADDUBSW SSSE3
instruction, but actually this refactoring by itself yields a 10%
speedup on texture intensive shaders (e.g, Google Earth's ocean water
w/o S3TC on a Ivy Bridge machine), while giving yielding exactly the
same results, whereas PMADDUBSW only gave an extra 5%, at the expense of
2bits of precision in the interpolation.

I belive that the speedup of this change comes from the reduced register
pressure (as 8.8 fixed point intermediates take twice the space of 8bit
unorm).

Also, not dealing with 8.8 simplifies lp_bld_sample_aos.c code
substantially -- it's no longer necessary to have code duplicated for
low and high register halfs.

Note about lp_build_sample_mipmap(): the path for num_quads > 1 is never
executed (as it is faster on AVX to split the 256bit wide texture
computation into two 128bit chunks, in order to leverage integer
opcodes).  This path might be useful in the future, so in order to
verify this change did not break that path I had to apply this change:

  @@ -1662,11 +1662,11 @@ lp_build_sample_soa(struct gallivm_state *gallivm,
         /*
          * we only try 8-wide sampling with soa as it appears to
          * be a loss with aos with AVX (but it should work).
          * (It should be faster if we'd support avx2)
          */
  -      if (num_quads == 1 || !use_aos) {
  +      if (/* num_quads == 1 || ! */ use_aos) {

            if (num_quads > 1) {
               if (mip_filter == PIPE_TEX_MIPFILTER_NONE) {
                  LLVMValueRef index0 = lp_build_const_int32(gallivm, 0);
                  /*

and then run texfilt mesademo:

  LP_NATIVE_VECTOR_WIDTH=256 ./texfilt

Ran whole piglit without regressions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-17 20:23:00 +01:00
Tom Stellard
e230d9debb radeon/llvm: Run standard optimization passes on conpute shader modules
The SROA and function inliner passes are espically important, because
they optimize away unsupported features: functions and indirect
private memory access.
2013-05-17 07:38:01 -07:00
Niels Ole Salscheider
7e17e72cb7 r600g: fixup for MSAA texture support checking
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
2013-05-16 12:03:47 -07:00
José Fonseca
4f518e1738 llvmpipe: Temporary workaround to prevent segfault on array textures. 2013-05-16 15:14:10 +01:00
Chia-I Wu
435aea6f32 ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+
Whether HiZ is enalbed or not, separate stencil is supported and enforced on
GEN7+.  Now that we support separate stencil resources, we know how to emit
3DSTATE_STENCIL_BUFFER.
2013-05-16 18:33:59 +08:00
Chia-I Wu
6b894e6900 ilo: add support for stencil resources on GEN7+
For allocations, we need to support stencil-only and separate stencil
resources.  For mapping, we need to support software tiling and
packing/unpacking for separate stencil resources.
2013-05-16 18:20:17 +08:00
Marek Olšák
5a3fac4d26 r600g: cleanup MSAA texture support checking
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15 20:20:32 +02:00
Marek Olšák
61c995bc47 r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samples
This fixes and enables texturing with compressed MSAA colorbuffers
on Evergreen and Cayman. For the first time, multisample textures work
on Cayman.

This requires the libdrm flag RADEON_SURF_FMASK.

v2: require libdrm_radeon 2.4.45

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15 20:19:45 +02:00
Chia-I Wu
c68424bac4 ilo: clean up transfer format conversion
Map the bo directly, instead of calling transfer_map().
2013-05-15 15:21:50 +08:00
Chia-I Wu
cb57da421a ilo: rework transfer mapping method choosing
Always check if a bo is busy in choose_transfer_method() since we always need
to map it in either map() or unmap().  Also determine how a bo is mapped in
choose_transfer_method().
2013-05-15 15:21:50 +08:00
Chia-I Wu
b6c307744f ilo: refactor transfer mapping
Add tex_get_box_offset() to compute transfer offet from the pipe_box.  Add
tex_get_slice_stride() to compute slice stride for a transfer.
2013-05-15 15:21:50 +08:00
Chia-I Wu
5af8641ce0 ilo: no writeback without PIPE_TRANSFER_WRITE
We should not write staging data back when PIPE_TRANSFER_WRITE is not set.
2013-05-15 15:08:54 +08:00
Chia-I Wu
46bb33bc21 ilo: minor cleanups for transfers
Rename some functions and reorder some code.
2013-05-15 15:08:54 +08:00
Chia-I Wu
ca349e0217 ilo: simplify ilo_texture_get_slice_offset()
Always return a tile-aligned offset.  Also fix for W tiling.
2013-05-15 15:08:54 +08:00
Zack Rusin
5104ed3dbf draw: try to prevent overflows on index buffers
Pass in the size of the index buffer, when available, and use it
to handle out of bounds conditions. The behavior in the case of
an overflow needs to be the same as with other overflows in the
vertex processing pipeline meaning that a vertex should still
be generated but all attributes in it set to zero.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:10:56 -04:00
Zack Rusin
29853ab7b8 draw: don't crash on vertex buffer overflow
We would crash when stride was bigger than the size of the buffer.
The correct behavior is to just fetch zero's in this case.
Unfortunatly with user_buffer's there's no way to validate the size
because currently we're just not getting it. Adjust the draw interface
to pass the size along the mapped buffer, which works perfectly
for buffer backed vertex_buffers and, in future, it will allow
us to plumb user_buffer sizes through the same interface.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-14 03:09:32 -04:00
Alex Deucher
d188f14941 radeonsi: update r600_get_llvm_processor_name for hainan
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-14 10:51:10 -04:00
Alex Deucher
4045c3d060 radeonsi: add support for hainan chips
Note: this is a candidate for the 9.1 branch

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-14 10:51:10 -04:00
Vadim Girlin
560ddad261 r600g/sb: add missing cases for ARUBA chips
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-14 17:36:25 +04:00
Vadim Girlin
ecde4b07e2 r600g/sb: get rid of standard c++ streams
Static initialization of internal libstdc++ data related to iostream
causes segfaults with some apps.

This patch replaces all uses of std::ostream and std::ostringstream in sb
with custom lightweight classes.

Prevents segfaults with ut2004demo and probably some other old apps.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-14 17:36:25 +04:00
Vadim Girlin
57d1be0d2d r600g/sb: separate bytecode decoding and parsing
Parsing and ir construction is required for optimization only,
it's unnecessary if we only need to print shader dump.
This should make new disassembler more tolerant to any new
features in the bytecode.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-14 17:36:25 +04:00
Chia-I Wu
176ad54c04 ilo: rework ilo_texture
Use ilo_buffer for buffer resources and ilo_texture for texture resources.  A
major cleanup is necessitated by the separation.
2013-05-14 16:07:22 +08:00