Commit graph

60134 commits

Author SHA1 Message Date
Ian Romanick
01bbebce4d mesa: Add missing checks for GL_TEXTURE_CUBE_MAP_ARRAY
That enum requires GL_ARB_texture_cube_map_array, and it is only
available on desktop GL.  It looks like this has been an un-noticed
issue since GL_ARB_texture_cube_map_array support was added in commit
e0e7e295.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-04 17:22:42 -08:00
Neil Roberts
5cddb1ce3c wayland: Add an extension to create wl_buffers from EGLImages
This adds an extension called EGL_WL_create_wayland_buffer_from_image
which adds the following single function:

struct wl_buffer *
eglCreateWaylandBufferFromImageWL(EGLDisplay dpy, EGLImageKHR image);

The function creates a wl_buffer which shares its contents with the given
EGLImage. The expected use case for this is in a nested Wayland compositor
which is using subsurfaces to present buffers from its clients. Using this
extension it can attach the client buffers directly to the subsurface without
having to blit the contents into an intermediate buffer. The compositing can
then be done in the parent compositor.

The extension is only implemented in the Wayland EGL platform because of
course it wouldn't make sense anywhere else.
2013-12-04 17:04:57 -08:00
Kristian Høgsberg
bce64c6c83 egl/wayland: Damage INT32_MAX x INT32_MAX region for eglSwapBuffers
If we're not using EGL_EXT_swap_buffers_with_damage, we have to
damage the full extent.  EGL operates on buffer coordinates, but
wl_surface.damage takes surface coordinates.  EGL doesn't know the
buffer transformation (rotated or scaled) and can't post accurate
damage in surface coordinates.  The damage event however is clipped to
the surface extents so we can just damage the maximum rectangle.

In case of EGL_EXT_swap_buffers_with_damage, the application knows
the buffer transform and is expected to pass in rectangles in
surface space.

https://bugs.freedesktop.org/show_bug.cgi?id=70250
Cc: "10.0" mesa-stable@lists.freedesktop.org
2013-12-04 16:13:42 -08:00
Axel Davy
afcce46fd5 Enable throttling in SwapBuffers
flush_with_flags, when available, allows the driver to throttle.
Using this suppress input lag issues that can be observed in heavy
rendering situations on non-intel cards.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Cc: "10.0" mesa-stable@lists.freedesktop.org
2013-12-04 15:58:29 -08:00
Kristian Høgsberg
33eb5eabee egl/wayland: Send commit after flushing the driver context
This typically won't make a difference, since we only send the requests at
wl_display_flush() time.  There might be a small race
with another thread calling wl_display_flush() after our commit request,
but before we flush the DRI driver.  Moving the commit below the DRI
driver flush call looks more natural and eliminates the small race.

Cc: "10.0" mesa-stable@lists.freedesktop.org
2013-12-04 15:48:28 -08:00
Axel Davy
402bf6e8d0 egl/wayland: Flush the wl_display at the end of SwapBuffers
We would like the compositor to receive the commited buffer
as soon as possible, so it has the time to treat it, and
release old ones. We shouldn't rely on the client
to flush the queue for us.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Cc: "10.0" mesa-stable@lists.freedesktop.org
2013-12-04 15:48:28 -08:00
Brian Paul
50205e11c6 mesa: reduce memory used for short display lists
Display lists allocate memory in chunks of 256 tokens (1KB) at a time.
If an app creates many short display lists or uses glXUseXFont() this
can waste quite a bit of memory.

This patch uses realloc() to trim short lists and reduce the memory
used.

Also, null/zero-out some list construction fields in _mesa_EndList().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-04 15:40:32 -07:00
Brian Paul
314ccf6901 mesa: update/remove display list comments
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-04 09:46:07 -07:00
Brian Paul
483dc973c4 mesa: remove gl_dlist_node::next pointer to reduce dlist memory use
Now, sizeof(gl_dlist_node)==4 even on 64-bit systems.  This can
halve the memory used by some display lists on 64-bit systems.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-04 09:46:07 -07:00
Brian Paul
b6468b4597 mesa: begin reducing memory used by display lists
This is a first step in reducing memory used by display lists on
64-bit systems.  On 64-bit systems, the gl_dlist_node union type
is 8 bytes because of the 'data' and 'next' fields.  This causes
every display list node/token to occupy 8 bytes instead of 4 as
originally designed.  This basically doubles the memory used by
some display lists on 64-bit systems.

The fix is to remove the 64-bit 'data' and 'next' pointer fields
from the union and instead store them as a pair of 32-bit values.
Easily done with a few helper functions.

The next patch will take care of the 'next' field.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-04 09:46:07 -07:00
Ilia Mirkin
06359e368b nouveau: Add lots of comments to the buffer transfer logic
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2013-12-04 16:38:50 +01:00
Ilia Mirkin
0e5bf85651 nv50: wait on the buf's fence before sticking it into pushbuf
This resolves some rendering issues in source games.
See https://bugs.freedesktop.org/show_bug.cgi?id=64323

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>
2013-12-04 16:38:50 +01:00
Ilia Mirkin
ce6dd69697 nouveau: avoid leaking fences while waiting
This fixes a memory leak in some situations. Also avoids emitting an
extra fence if the kick handler does the call to nouveau_fence_next
itself.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>
2013-12-04 16:38:50 +01:00
Ilia Mirkin
f50a45452a nv50: fix a small leak on context destroy
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2013-12-04 16:38:50 +01:00
Brian Paul
657466a3f6 docs: put MD5 sums in 9.2.4 relnotes file
Signed-off-by: Brian Paul <brianp@vmware.com>
2013-12-04 07:47:13 -07:00
Brian Paul
2732d0d21d docs: use --disable-dri3 for VMware guest driver build
For the time being at least.  Suggested by Adrian Rangel.

Signed-off-by: Brian Paul <brianp@vmware.com>
2013-12-04 07:41:29 -07:00
Siavash Eliasi
f0cc59d68a mesa: modified _mesa_align_free() to accept NULL pointer
So that it acts like ordinary free().  This lets us remove a bunch of
if statements where the function is called.

v2:
- Avoiding compile error on MSVC and possible warnings on other compilers.
- Added comment regards passing NULL pointer being safe.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-04 07:31:27 -07:00
Ilia Mirkin
267679be84 mesa: don't leak performance monitors on context destroy
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-04 06:20:36 -08:00
Ilia Mirkin
c45cf6199f nv50: Fix GPU_READING/WRITING bit removal
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
CC: "9.1, 9.2, 10.0" <mesa-stable@lists.freedesktop.org>
2013-12-04 14:24:30 +01:00
Michel Dänzer
79e6512629 pipe-loader: Fix llvmpipe.la path
Fixes

 make[3]: *** No rule to make target `.../src/gallium/drivers/softpipe/libllvmpipe.la', needed by `pipe_swrast.la'.  Stop.
2013-12-04 11:56:10 +09:00
Kenneth Graunke
26b7b50afe i965: Fix BRW_BATCH_STRUCT to specify RENDER_RING, not UNKNOWN_RING.
I missed this in the boolean -> enum conversion.  C cheerfully casts
false -> 0 -> UNKNOWN_RING.  On Gen4-5, this causes the render ring
prelude hook to get called in the middle of the batch, which is crazy.

BRW_BATCH_STRUCT is not used on Gen6+.

Fixes regressions since 395a32717d
("i965: Introduce an UNKNOWN_RING state.").

Fixes "fips -v glxgears" on Ironlake.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-03 16:24:58 -08:00
Kenneth Graunke
e03994bf47 Revert "i965: Move brw_emit_query_begin() to the render ring prelude."
This reverts commit a4bf7f6b6e.
It breaks occlusion queries on Gen4-5.  Doing this right will likely
require larger changes, which should be done at a future date.

Some Piglit tests still passed due to other bugs; fixing those revealed
this problem.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-03 16:24:53 -08:00
Kenneth Graunke
da07e1b683 i965: Fix OACONTROL assertion failures on Ironlake.
I guarded half of the callers to start/stop_oa_counters with generation
checks, but missed the other half (which were added later).  OACONTROL
doesn't exist on Ironlake, so we better not write it.  Also, there's no
need---Ironlake's performance counters are always running.

This patch moves the generation checks into start/stop_oa_counters,
rather than requiring the caller to do them.

Fixes assertion failures in Piglit's AMD_performance_monitor/measure.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-03 16:24:49 -08:00
Emil Velikov
4c11099453 gallium/radeon: use PRIu64 macro for printing uint64_t
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-12-03 21:44:26 +00:00
Emil Velikov
f60737a525 pipe-loader: build llvmpipe on top of softpipe
One can select if they want to fallback to softpipe.
Current approach makes this not possible, whereas other
targets (dri-swrast) handle this approapriately.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-12-03 21:44:26 +00:00
Emil Velikov
bc2627a98a mesa: resolve typo DTXn/DXTn
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-12-03 21:44:26 +00:00
Emil Velikov
507c2356e3 automake: include only one copy VERSION in tarball
The VERSION file is tracked by git (git ls-files), thus
adding it to EXTRA_FILES will result in a duplicate copy
within the final tarball.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72230
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reported-by: Patrick Steinhardt <ps@pks.im>
Tested-by: Patrick Steinhardt <ps@pks.im>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-12-03 21:44:26 +00:00
Juha-Pekka Heikkila
03ef57950a glx: Add missing null check in gxl/dri2_glx.c
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-03 14:35:41 -07:00
Juha-Pekka Heikkila
b8875cb7c8 glx: Check malloc return value before accessing memory in glx/clientattrib.c
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-03 14:35:41 -07:00
Chad Versace
998018d7be i965: Add extra-alignment for non-msrt fast color clear for all hw (v2)
The BSpec states that the aligment for the non-msrt clear rectangle must
be doubled; the BSpec does not restricit the workaround to specific
hardware.

Commit 9a1a67b applied the workaround to Haswell GT3.  Commit 8b659ce
expanded the workaround to all Haswell variants. This commit expands it
to all hardware.

No Piglit regressions on Ivybridge 0x0166. No fixes either.

I know no Ivybridge nor Baytrail bug related to this workaround.
However, the BSpec says the extra alignment is required, so let's do it.

v2: Apply to all hardware, not just gen7.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-12-03 13:19:54 -08:00
Marek Olšák
40e2856123 configure.ac: require libdrm_radeon 2.4.50 2013-12-03 20:07:35 +01:00
Marek Olšák
e47af58bb4 st/mesa: implement layered framebuffer clear for the clear_with_quad fallback
Same approach as in u_blitter.
2013-12-03 19:39:13 +01:00
Marek Olšák
6b919b1b2d gallium/util: implement layered framebuffer clear in u_blitter
All bound layers (from first_layer to last_layer) should be cleared.

This uses a vertex shader which outputs gl_Layer = gl_InstanceID, so each
instance goes to a different layer. By rendering a quad and setting
the instance count to the number of layers, it will trivially clear all
layers.

This requires AMD_vertex_shader_layer (or PIPE_CAP_TGSI_VS_LAYER), which only
radeonsi supports at the moment. r600 could do this too. Standard DX11
hardware will have to use a geometry shader though, which has higher overhead.
2013-12-03 19:39:13 +01:00
Marek Olšák
1a02bb71dd gallium: add support for AMD_vertex_shader_layer 2013-12-03 19:39:13 +01:00
Marek Olšák
d52791a708 radeonsi: add driver support for layered rendering and AMD_vertex_shader_layer
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-03 19:39:13 +01:00
Marek Olšák
053606ddae radeonsi: implement OpenGL edge flags
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-03 19:39:13 +01:00
Marek Olšák
d8d67d2e1f st/mesa: add support for layered framebuffers and consolidate code
This is a subset of geometry shaders. It's all about setting first_layer and
last_layer correctly.

Also some code between st_render_texture and update_framebuffer_state is
consolidated. It doesn't use rtt_level and derives the level from dimensions
instead as the code in st_atom_framebuffer.c did.
2013-12-03 19:39:13 +01:00
Marek Olšák
0b3b901cff mesa: expose AMD_vertex_shader_layer in the core profile only
It needs glFramebufferTexture, which isn't available in the compatibility
profile.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-03 19:39:13 +01:00
Tapani Pälli
a057b837dd egl: add HAVE_LIBDRM define, fix EGL X11 platform
Commit a594cec broke EGL X11 backend by adding dependency between
X11 and DRM backends requiring HAVE_EGL_PLATFORM_DRM defined for X11.

This patch fixes the issue by adding additional define for libdrm
detection independent of which backend is being compiled. Tested by
compiling Mesa with '--with-egl-platforms=x11' and running es2gears_x11
+ glbenchmark2.7 successfully.

v2: return true for dri2_auth if running without libdrm (Samuel)
v3: check libdrm when building EGL drm platform + AM_CFLAGS fix (Emil)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72062
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Cc: Samuel Thibault <samuel.thibault@ens-lyon.org>
Cc: mesa-stable@lists.freedesktop.org
2013-12-03 09:21:24 -08:00
Andreas Heider
ad3937fd4e freedreno: Add a few texture formats 2013-12-02 17:37:03 -05:00
Kenneth Graunke
decf070258 i965: Skip the register write check on Broadwell.
MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work.  But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-02 13:26:03 -08:00
Kenneth Graunke
8ed9f69b36 i965: Fix texture border color on Broadwell.
The Gen7 sampler state code still works.  Increasing the alignment to
64 bytes makes bit 5 zero, which is good because it's now reserved.

Since we don't use the new filter bits, we can leave those as zero too,
which means we don't need to update the code to update the pointer.
(We probably should anyway, for clarity, but alas, another day.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-02 13:25:52 -08:00
Kenneth Graunke
bc9d3a0254 i965: Don't use MACH for integer multiplies on Gen8+.
The documentation is really hard to follow, but apparently a 32-bit x
32-bit multiply just works without the MACH macro.  The macro apparently
is only necessary to get the full 64-bit value.

Fixes Piglit tests [vf]s-op-mult-int-int.shader_test.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-02 13:25:32 -08:00
Kenneth Graunke
5720832f23 i965: Fix texture swizzling on Broadwell.
Like Haswell, we do this in SURFACE_STATE rather than shader
workarounds.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-02 13:25:23 -08:00
Kenneth Graunke
1110ba4c08 i965: Set vertical alignment unit to 4 on Broadwell.
Broadwell doesn't support a surface vertical alignment of 2.  It only
supports VALIGN_4, VALIGN_8, or VALIGN_16.  I chose 4 since it's the
least wasteful.

v2: Replace my comment with a better one from Eric.  Move Broadwell
    checks earlier so it's more obvious that "return 2" won't be hit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-02 13:25:11 -08:00
Kenneth Graunke
93658054c0 i965/vs: Always store pull constant offsets in GRFs on Gen8.
We need to SEND from a GRF, and we can only obtain those prior to
register allocation.

This allows us to do pull constant loads without the MRF hack.

v2: Reword comments (suggested by Paul).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-02 13:19:10 -08:00
Kenneth Graunke
dd159f25e4 i965/vs: Don't copy propagate into SEND-from-GRF messages.
SEND can't deal with swizzles, source modifiers, and so on.  This should
avoid problems with VS pull constant loads on Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-02 13:10:12 -08:00
Francisco Jerez
ce34158680 clover: Fix missing minus sign in 'iterator_adaptor::operator-='.
The method is currently unused, this probably doesn't fix anything at
this point.
2013-12-02 11:55:02 -08:00
Chad Versace
8b659cef3a i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTs
Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.

Also, update the BSpec quote that discusses the workaround to reflect
the latest BSpec.

The BSpec states that the workaround is required for Ivybridge and
Baytrail as well as Haswell. But, we apply the workaround to only
Haswell because (a) we suspect that is the only hardware where it is
actually required and (b) we haven't yet validated the workaround for
the other hardware.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
OTC-Tracker: CHRMOS-812
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-12-02 10:53:33 -08:00
Kenneth Graunke
5b331f6fcb glsl: Simplify the built-in function linking code.
Previously, we stored an array of up to 16 additional shaders to link,
as well as a count of how many each shader actually needed.

Since the built-in functions rewrite, all the built-ins are stored in a
single shader.  So all we need is a boolean indicating whether a shader
needs to link against built-ins or not.

During linking, we can avoid creating the temporary array if none of the
shaders being linked need built-ins.  Otherwise, it's simply a copy of
the array that has one additional element.  This is much simpler.

This patch saves approximately 128 bytes of memory per gl_shader object.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-01 15:33:04 -08:00