mesa/src/amd
Natalie Vock 71145cb846 radv/nir: Correctly handle workgroup sizes not aligned to 32
Since the stride is always 32 dwords, we need to treat the workgroup
size as multiples of that value. Using MAX2() only works for cases where
the workgroup size is less than 32, which was hit by some CTS with 1x1
workgroups.

Cc: mesa-stable
(cherry picked from commit b08f9f192c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
2026-02-25 14:22:22 +01:00
..
addrlib amd: rename most GFX115x definitions for released chips 2025-12-03 13:29:07 +00:00
ci ac/nir: fix computing cube derivatives when the major axis is negative 2026-01-21 07:12:34 +00:00
common ac,radv,radeonsi: use correct swizzle/pitch for depth-only images with SDMA 2026-02-25 14:22:20 +01:00
compiler aco: fix gfx6-8 store_scratch() with function calls 2026-02-25 14:22:22 +01:00
drm-shim amd/drm-shim: add vega20 2026-01-08 09:30:54 +00:00
gmlib meson: Relax -Wmaybe-uninitialized errors 2025-09-16 06:16:20 +00:00
lanczoslib meson: Relax -Wmaybe-uninitialized errors 2025-09-16 06:16:20 +00:00
llvm amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug 2025-12-22 07:34:48 +00:00
registers amd: Rename GFX1103_R1/R2 to PHOENIX/2 2024-11-20 02:14:40 +00:00
vpelib amd/vpelib: add FL capabilitie and lut container size 2025-09-22 10:37:22 +00:00
vulkan radv/nir: Correctly handle workgroup sizes not aligned to 32 2026-02-25 14:22:22 +01:00
meson.build radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY 2025-11-19 07:11:05 +00:00