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amd: Rename GFX1103_R1/R2 to PHOENIX/2

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This is to match the code names used in other enums.
Also add comments to separate GFX11.5 and GFX12 chips.

v2 by Marek Olšák:
- Rename GFX1103 to in addrlib also
- Rework ac_get_family_name

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32170>
This commit is contained in:
Timur Kristóf 2024-11-16 14:12:55 +01:00 • committed by Marge Bot
parent d918edaf9a
commit c294e7f138
10 changed files with 78 additions and 122 deletions
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19
src/amd/addrlib/src/amdgpu_asic_addr.h
View file

@ -28,7 +28,7 @@
#define FAMILY_VGH 0x90 //# 144 / Van Gogh
#define FAMILY_NV3 0x91 //# 145 / Navi: 3x
#define FAMILY_GFX1150 0x96
#define FAMILY_GFX1103 0x94
#define FAMILY_PHX 0x94 //# 148 / Phoenix
#define FAMILY_RMB 0x92 //# 146 / Rembrandt
#define FAMILY_RPL 0x95 //# 149 / Raphael
#define FAMILY_MDN 0x97 //# 151 / Mendocino
@ -103,11 +103,10 @@
#define AMDGPU_GFX1150_RANGE 0x01, 0x40 //# 1 <= x < 64
#define AMDGPU_GFX1151_RANGE 0xC0, 0xFF //# 192 <= x < 255
#define AMDGPU_GFX1152_RANGE 0x40, 0x50 //# 64 <= x < 80
#define AMDGPU_GFX1103_R1_RANGE 0x01, 0x80 //# 1 <= x < 128
#define AMDGPU_GFX1103_R2_RANGE 0x80, 0xC0 //# 128 <= x < 192
#define AMDGPU_GFX1103_R1X_RANGE 0xC0, 0xF0 //# 192 <= x < 240
#define AMDGPU_GFX1103_R2X_RANGE 0xF0, 0xFF //# 240 <= x < 255
#define AMDGPU_PHOENIX1_RANGE 0x01, 0x80 //# 1 <= x < 128
#define AMDGPU_PHOENIX2_RANGE 0x80, 0xC0 //# 128 <= x < 192
#define AMDGPU_HAWK_POINT1_RANGE 0xC0, 0xF0 //# 192 <= x < 240
#define AMDGPU_HAWK_POINT2_RANGE 0xF0, 0xFF //# 240 <= x < 255
#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF //# 01 <= x < 255
#define AMDGPU_RAPHAEL_RANGE 0x01, 0xFF //# 1 <= x < max
@ -183,10 +182,10 @@
#define ASICREV_IS_GFX1151(r) ASICREV_IS(r, GFX1151)
#define ASICREV_IS_GFX1152(r) ASICREV_IS(r, GFX1152)
#define ASICREV_IS_GFX1103_R1(r) ASICREV_IS(r, GFX1103_R1)
#define ASICREV_IS_GFX1103_R2(r) ASICREV_IS(r, GFX1103_R2)
#define ASICREV_IS_GFX1103_R1X(r) ASICREV_IS(r, GFX1103_R1X)
#define ASICREV_IS_GFX1103_R2X(r) ASICREV_IS(r, GFX1103_R2X)
#define ASICREV_IS_PHOENIX1(r) ASICREV_IS(r, PHOENIX1)
#define ASICREV_IS_PHOENIX2(r) ASICREV_IS(r, PHOENIX2)
#define ASICREV_IS_HAWK_POINT1(r) ASICREV_IS(r, HAWK_POINT1)
#define ASICREV_IS_HAWK_POINT2(r) ASICREV_IS(r, HAWK_POINT2)
#define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT)
#define ASICREV_IS_RAPHAEL(r) ASICREV_IS(r, RAPHAEL)

2
src/amd/addrlib/src/core/addrlib.cpp
View file

@ -221,7 +221,7 @@ ADDR_E_RETURNCODE Lib::Create(
break;
case FAMILY_NV3:
case FAMILY_GFX1150:
case FAMILY_GFX1103:
case FAMILY_PHX:
pLib = Gfx11HwlInit(&client);
break;
case FAMILY_GFX12:

6
src/amd/addrlib/src/gfx11/gfx11addrlib.cpp
View file

@ -751,8 +751,8 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily(
m_settings.isGfx1150 = 1;
}
break;
case FAMILY_GFX1103:
m_settings.isGfx1103 = 1;
case FAMILY_PHX:
m_settings.isPhoenix = 1;
break;
default:
ADDR_ASSERT(!"Unknown chip family");
@ -1751,7 +1751,7 @@ UINT_32 Gfx11Lib::GetValidDisplaySwizzleModes(
swModeMask = Dcn32SwModeMask;
if (false
|| (m_settings.isGfx1103)
|| (m_settings.isPhoenix)
|| (m_settings.isGfx1150)
)
{

2
src/amd/addrlib/src/gfx11/gfx11addrlib.h
View file

@ -35,7 +35,7 @@ struct Gfx11ChipSettings
struct
{
UINT_32 isGfx1150 : 1;
UINT_32 isGfx1103 : 1;
UINT_32 isPhoenix : 1;
UINT_32 reserved1 : 30;
// Misc configuration bits

2
src/amd/common/ac_descriptors.c
View file

@ -1409,7 +1409,7 @@ ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac
cb->cb_dcc_control |= S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) |
S_028C78_FDCC_ENABLE(1);
if (info->family >= CHIP_GFX1103_R2) {
if (info->family >= CHIP_PHOENIX2) {
cb->cb_dcc_control |= S_028C78_ENABLE_MAX_COMP_FRAG_OVERRIDE(1) |
S_028C78_MAX_COMP_FRAGS(state->num_samples >= 4);
}

12
src/amd/common/ac_gpu_info.c
View file

@ -895,11 +895,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
identify_chip(NAVI32);
identify_chip(NAVI33);
break;
case FAMILY_GFX1103:
identify_chip(GFX1103_R1);
identify_chip(GFX1103_R2);
identify_chip2(GFX1103_R1X, GFX1103_R1);
identify_chip2(GFX1103_R2X, GFX1103_R2);
case FAMILY_PHX:
identify_chip2(PHOENIX1, PHOENIX);
identify_chip(PHOENIX2);
identify_chip2(HAWK_POINT1, PHOENIX);
identify_chip2(HAWK_POINT2, PHOENIX2);
break;
case FAMILY_GFX1150:
identify_chip(GFX1150);
@ -1188,7 +1188,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->l2_cache_size = info->num_tcc_blocks * 256 * 1024;
break;
case CHIP_REMBRANDT:
case CHIP_GFX1103_R1:
case CHIP_PHOENIX:
info->l2_cache_size = info->num_tcc_blocks * 512 * 1024;
break;
}

147
src/amd/common/amd_family.c
View file

@ -16,100 +16,55 @@
const char *ac_get_family_name(enum radeon_family family)
{
switch (family) {
case CHIP_TAHITI:
return "TAHITI";
case CHIP_PITCAIRN:
return "PITCAIRN";
case CHIP_VERDE:
return "VERDE";
case CHIP_OLAND:
return "OLAND";
case CHIP_HAINAN:
return "HAINAN";
case CHIP_BONAIRE:
return "BONAIRE";
case CHIP_KABINI:
return "KABINI";
case CHIP_KAVERI:
return "KAVERI";
case CHIP_HAWAII:
return "HAWAII";
case CHIP_TONGA:
return "TONGA";
case CHIP_ICELAND:
return "ICELAND";
case CHIP_CARRIZO:
return "CARRIZO";
case CHIP_FIJI:
return "FIJI";
case CHIP_STONEY:
return "STONEY";
case CHIP_POLARIS10:
return "POLARIS10";
case CHIP_POLARIS11:
return "POLARIS11";
case CHIP_POLARIS12:
return "POLARIS12";
case CHIP_VEGAM:
return "VEGAM";
case CHIP_VEGA10:
return "VEGA10";
case CHIP_RAVEN:
return "RAVEN";
case CHIP_VEGA12:
return "VEGA12";
case CHIP_VEGA20:
return "VEGA20";
case CHIP_RAVEN2:
return "RAVEN2";
case CHIP_RENOIR:
return "RENOIR";
case CHIP_MI100:
return "MI100";
case CHIP_MI200:
return "MI200";
case CHIP_GFX940:
return "GFX940";
case CHIP_NAVI10:
return "NAVI10";
case CHIP_NAVI12:
return "NAVI12";
case CHIP_NAVI14:
return "NAVI14";
case CHIP_NAVI21:
return "NAVI21";
case CHIP_NAVI22:
return "NAVI22";
case CHIP_NAVI23:
return "NAVI23";
case CHIP_VANGOGH:
return "VANGOGH";
case CHIP_NAVI24:
return "NAVI24";
case CHIP_REMBRANDT:
return "REMBRANDT";
case CHIP_RAPHAEL_MENDOCINO:
return "RAPHAEL_MENDOCINO";
case CHIP_NAVI31:
return "NAVI31";
case CHIP_NAVI32:
return "NAVI32";
case CHIP_NAVI33:
return "NAVI33";
case CHIP_GFX1103_R1:
return "GFX1103_R1";
case CHIP_GFX1103_R2:
return "GFX1103_R2";
case CHIP_GFX1150:
return "GFX1150";
case CHIP_GFX1151:
return "GFX1151";
case CHIP_GFX1152:
return "GFX1152";
case CHIP_GFX1200:
return "GFX1200";
case CHIP_GFX1201:
return "GFX1201";
#define CASE(name) case CHIP_##name: return #name
CASE(TAHITI);
CASE(PITCAIRN);
CASE(VERDE);
CASE(OLAND);
CASE(HAINAN);
CASE(BONAIRE);
CASE(KABINI);
CASE(KAVERI);
CASE(HAWAII);
CASE(TONGA);
CASE(ICELAND);
CASE(CARRIZO);
CASE(FIJI);
CASE(STONEY);
CASE(POLARIS10);
CASE(POLARIS11);
CASE(POLARIS12);
CASE(VEGAM);
CASE(VEGA10);
CASE(RAVEN);
CASE(VEGA12);
CASE(VEGA20);
CASE(RAVEN2);
CASE(RENOIR);
CASE(MI100);
CASE(MI200);
CASE(GFX940);
CASE(NAVI10);
CASE(NAVI12);
CASE(NAVI14);
CASE(NAVI21);
CASE(NAVI22);
CASE(NAVI23);
CASE(VANGOGH);
CASE(NAVI24);
CASE(REMBRANDT);
CASE(RAPHAEL_MENDOCINO);
CASE(NAVI31);
CASE(NAVI32);
CASE(NAVI33);
CASE(PHOENIX);
CASE(PHOENIX2);
CASE(GFX1150);
CASE(GFX1151);
CASE(GFX1152);
CASE(GFX1200);
CASE(GFX1201);
#undef CASE
default:
unreachable("Unknown GPU family");
}
@ -243,8 +198,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
return "gfx1101";
case CHIP_NAVI33:
return "gfx1102";
case CHIP_GFX1103_R1:
case CHIP_GFX1103_R2:
case CHIP_PHOENIX:
case CHIP_PHOENIX2:
return "gfx1103";
case CHIP_GFX1150:
return "gfx1150";

6
src/amd/common/amd_family.h
View file

@ -119,11 +119,13 @@ enum radeon_family
CHIP_NAVI31, /* Radeon 7900 */
CHIP_NAVI32, /* Radeon 7800, 7700 */
CHIP_NAVI33, /* Radeon 7600, 7700S (mobile) */
CHIP_GFX1103_R1,
CHIP_GFX1103_R2,
CHIP_PHOENIX, /* Ryzen Z1 Extreme, Ryzen 7040, Ryzen 8040 */
CHIP_PHOENIX2, /* Ryzen Z1, Ryzen 8040 */
/* GFX11.5 (RDNA 3.5) */
CHIP_GFX1150,
CHIP_GFX1151,
CHIP_GFX1152,
/* GFX12 (RDNA 4) */
CHIP_GFX1200,
CHIP_GFX1201,
CHIP_LAST,

2
src/amd/registers/parse_kernel_headers.py
View file

@ -780,7 +780,7 @@ fields_missing = {
},
'gfx11': {
"VGT_DRAW_PAYLOAD_CNTL": [["EN_VRS_RATE", 6, 6]],
# Only GFX1103_R2:
# Only Phoenix2:
"CB_COLOR0_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25],
["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26],
["MAX_COMP_FRAGS", 27, 29]],

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -1406,7 +1406,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->info.gfx_level >= GFX10) {
/* Only bin draws that have no CONTEXT and SH register changes between
* them because higher settings cause hangs. We've only been able to
* reproduce hangs on smaller chips (e.g. Navi24, GFX1103), though all
* reproduce hangs on smaller chips (e.g. Navi24, Phoenix), though all
* chips might have them. What we see may be due to a driver bug.
*/
sscreen->pbb_context_states_per_bin = 1;