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amd/drm-shim: add vega20

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Vega20 ISA is different enough from Vega10 that having it
in drm-shim is useful for testing compiler changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39188>
This commit is contained in:
Georg Lehmann 2026-01-07 11:52:53 +01:00 • committed by Marge Bot
parent bfa8dcf3b3
commit 330e88abb8
1 changed files with 129 additions and 0 deletions
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129
src/amd/drm-shim/amdgpu_devices.c
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@ -2313,6 +2313,135 @@ const struct amdgpu_device amdgpu_devices[] = {
},
},
},
{
.name = "vega20",
.radeon_family = CHIP_VEGA20,
.hw_ip_gfx = {
.hw_ip_version_major = 9,
.hw_ip_version_minor = 0,
.capabilities_flags = UINT64_C(0),
.ib_start_alignment = 32,
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0x90400,
},
.hw_ip_compute = {
.hw_ip_version_major = 9,
.hw_ip_version_minor = 0,
.capabilities_flags = UINT64_C(0),
.ib_start_alignment = 32,
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0x90400,
},
.fw_gfx_me = {
.ver = 167,
.feature = 54,
},
.fw_gfx_pfp = {
.ver = 195,
.feature = 54,
},
.fw_gfx_mec = {
.ver = 471,
.feature = 54,
},
.mmr_regs = {
0x263e, 0xffffffff, 0x2a114042,
},
.mmr_reg_count = 1,
.dev = {
.device_id = 0x66a1,
.chip_rev = 0x01,
.external_rev = 0x29,
.pci_rev = 0x06,
.family = AMDGPU_FAMILY_AI,
.num_shader_engines = 4,
.num_shader_arrays_per_engine = 1,
.gpu_counter_freq = 25000,
.max_engine_clock = UINT64_C(1700000),
.max_memory_clock = UINT64_C(1000000),
.cu_active_number = 60,
.cu_ao_mask = 0xfffefffe,
.cu_bitmap = {
{ 0xfffe, 0x0, 0x0, 0x0, },
{ 0xfffe, 0x0, 0x0, 0x0, },
{ 0xfffd, 0x0, 0x0, 0x0, },
{ 0xfffe, 0x0, 0x0, 0x0, },
},
.enabled_rb_pipes_mask = 0xffff,
.num_rb_pipes = 16,
.num_hw_gfx_contexts = 8,
.pcie_gen = 4,
.ids_flags = UINT64_C(0x0),
.virtual_address_offset = UINT64_C(0x200000),
.virtual_address_max = UINT64_C(0x800000000000),
.virtual_address_alignment = 4096,
.pte_fragment_size = 2097152,
.gart_page_size = 4096,
.ce_ram_size = 32768,
.vram_type = 6,
.vram_bit_width = 4096,
.vce_harvest_config = 0,
.gc_double_offchip_lds_buf = 1,
.prim_buf_gpu_addr = UINT64_C(0),
.pos_buf_gpu_addr = UINT64_C(0),
.cntl_sb_buf_gpu_addr = UINT64_C(0),
.param_buf_gpu_addr = UINT64_C(0),
.prim_buf_size = 0,
.pos_buf_size = 0,
.cntl_sb_buf_size = 0,
.param_buf_size = 0,
.wave_front_size = 64,
.num_shader_visible_vgprs = 256,
.num_cu_per_sh = 16,
.num_tcc_blocks = 2,
.gs_vgt_table_depth = 32,
.gs_prim_buffer_depth = 1792,
.max_gs_waves_per_vgt = 32,
.pcie_num_lanes = 16,
.cu_ao_bitmap = {
{ 0x1ffe, 0x0, 0x0, 0x0, },
{ 0x1ffe, 0x0, 0x0, 0x0, },
{ 0x1ffd, 0x0, 0x0, 0x0, },
{ 0x1ffe, 0x0, 0x0, 0x0, },
},
.high_va_offset = UINT64_C(0xffff800000000000),
.high_va_max = UINT64_C(0xffffffffffe00000),
.pa_sc_tile_steering_override = 0,
.tcc_disabled_mask = UINT64_C(0),
.min_engine_clock = UINT64_C(859000),
.min_memory_clock = UINT64_C(350000),
.tcp_cache_size = 0,
.num_sqc_per_wgp = 0,
.sqc_data_cache_size = 0,
.sqc_inst_cache_size = 0,
.gl1c_cache_size = 0,
.gl2c_cache_size = 0,
.mall_size = UINT64_C(0),
.enabled_rb_pipes_mask_hi = 0,
},
.mem = {
.vram = {
.total_heap_size = UINT64_C(17163091968),
.usable_heap_size = UINT64_C(17143853056),
.heap_usage = UINT64_C(10862592),
.max_allocation = UINT64_C(12857889792),
},
.cpu_accessible_vram = {
.total_heap_size = UINT64_C(17163091968),
.usable_heap_size = UINT64_C(17143853056),
.heap_usage = UINT64_C(10862592),
.max_allocation = UINT64_C(12857889792),
},
.gtt = {
.total_heap_size = UINT64_C(67463200768),
.usable_heap_size = UINT64_C(67448295424),
.heap_usage = UINT64_C(14917632),
.max_allocation = UINT64_C(50586221568),
},
},
}
};
const size_t num_amdgpu_devices = ARRAY_SIZE(amdgpu_devices);