Alejandro Piñeiro a4031bdfa9 i965/fs: Predicate byte scattered writes if needed ... While on Untyped Surface messages the bits of the execution mask are ANDed with the corresponding bits of the Pixel/Sample Mask, that is not the case for byte scattered writes. That is needed to avoid ssbo stores writing on helper invocations. So when that can affect, we load the sample mask, and predicate the send message. Note: the need for this patch was tested with a custom test. Right now the 16 bit storage CTS tests doesnt need this path in order to get a full pass. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>		2017-12-06 08:57:18 +01:00
..
.gitignore
brw_cfg.cpp
brw_cfg.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_clip.h	i965: Move clip program compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_clip_line.c	i965: Move clip program compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_clip_point.c	i965: Move clip program compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_clip_tri.c	i965: Move clip program compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_clip_unfilled.c	i965: Move clip program compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_clip_util.c	i965: Move clip program compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_compile_clip.c	i965: Rewrite disassembly annotation code	2017-11-17 12:14:38 -08:00
brw_compile_sf.c	i965: Move SF compilation to the compiler	2017-05-26 07:58:01 -07:00
brw_compiler.c	nir/lower_subgroups: Lower ballot intrinsics to the specified bit size	2017-11-07 10:37:52 -08:00
brw_compiler.h	intel: Drop mtypes.h include from brw_compiler.h.	2017-11-15 09:37:32 -08:00
brw_dead_control_flow.cpp
brw_dead_control_flow.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_disasm.c	i965: Add align1 ternary instruction disassembler support	2017-10-20 15:00:17 -07:00
brw_disasm_info.c	i965: Rename intel_asm_annotation -> brw_disasm_info	2017-11-17 12:14:38 -08:00
brw_disasm_info.h	i965: Stop including brw_cfg.h in brw_disasm_info.h	2017-11-17 21:51:16 -08:00
brw_eu.c	intel/eu: Make automatic exec sizes a configurable option	2017-11-07 10:37:52 -08:00
brw_eu.h	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_eu_compact.c	i965: Rename intel_asm_annotation -> brw_disasm_info	2017-11-17 12:14:38 -08:00
brw_eu_defines.h	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_eu_emit.c	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_eu_util.c	intel/compiler: whitespace cleanups	2017-03-13 11:16:35 +00:00
brw_eu_validate.c	i965: Rewrite disassembly annotation code	2017-11-17 12:14:38 -08:00
brw_fs.cpp	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_fs.h	i965/fs: Add remove_extra_rounding_modes optimization	2017-12-06 08:57:18 +01:00
brw_fs_builder.h
brw_fs_cmod_propagation.cpp	intel/compiler: Don't propagate cmod into integer multiplies	2017-10-05 11:54:49 -07:00
brw_fs_combine_constants.cpp
brw_fs_copy_propagation.cpp	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_fs_cse.cpp
brw_fs_dead_code_eliminate.cpp
brw_fs_generator.cpp	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_fs_live_variables.cpp
brw_fs_live_variables.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_fs_lower_conversions.cpp	i965/fs: rename lower_d2x to lower_conversions	2017-04-14 14:56:07 -07:00
brw_fs_lower_pack.cpp
brw_fs_nir.cpp	i965/fs: Predicate byte scattered writes if needed	2017-12-06 08:57:18 +01:00
brw_fs_reg_allocate.cpp	intel/fs: Take into account amount of data read in spilling cost heuristic.	2017-04-24 11:01:40 -07:00
brw_fs_register_coalesce.cpp
brw_fs_saturate_propagation.cpp	i965/fs: Handle negating immediates on MADs when propagating saturates	2017-11-21 10:13:07 -08:00
brw_fs_sel_peephole.cpp	i965/fs: Do not move MOVs writing the flag outside of control flow	2017-07-20 16:56:49 -07:00
brw_fs_surface_builder.cpp	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_fs_surface_builder.h	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_fs_validate.cpp
brw_fs_visitor.cpp	intel/fs: Explicitly set EXECUTE_1 where needed	2017-11-07 10:37:52 -08:00
brw_inst.h	i965: Add align1 ternary instruction-word support	2017-10-20 15:00:17 -07:00
brw_interpolation_map.c
brw_ir_allocator.h
brw_ir_fs.h	i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type	2017-12-06 08:57:18 +01:00
brw_ir_vec4.h	i965/vec4: don't do horizontal stride on some register file types	2017-04-14 14:56:09 -07:00
brw_nir.c	i965: Support for 16-bit base types in helper functions	2017-12-06 08:57:18 +01:00
brw_nir.h	intel/nir: Break the linking code into a helper in brw_nir.c	2017-11-08 14:09:51 -08:00
brw_nir_analyze_boolean_resolves.c
brw_nir_analyze_ubo_ranges.c	nir: Get rid of nir_shader::stage	2017-10-20 12:49:17 -07:00
brw_nir_attribute_workarounds.c	nir: Rework conversion opcodes	2017-03-14 07:36:40 -07:00
brw_nir_lower_cs_intrinsics.c	intel/cs: Push subgroup ID instead of base thread ID	2017-11-07 10:37:52 -08:00
brw_nir_opt_peephole_ffma.c
brw_nir_tcs_workarounds.c	nir: Get rid of nir_shader::stage	2017-10-20 12:49:17 -07:00
brw_nir_trig_workarounds.py	intel: use a flag instead of setting PYTHONPATH	2017-09-27 09:07:28 -07:00
brw_packed_float.c
brw_predicated_break.cpp
brw_reg.h	i965: Add support for control register	2017-12-06 08:57:18 +01:00
brw_reg_type.c	i965: Add align1 ternary instruction support to conversion functions	2017-10-20 15:00:17 -07:00
brw_reg_type.h	i965: Add align1 ternary instruction support to conversion functions	2017-10-20 15:00:17 -07:00
brw_schedule_instructions.cpp	i965: Use is_scheduling_barrier instead of schedule_node::is_barrier.	2017-10-19 10:19:20 -07:00
brw_shader.cpp	i965/fs: Add byte scattered write message and fs support	2017-12-06 08:57:18 +01:00
brw_shader.h	i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.	2017-11-15 09:37:32 -08:00
brw_vec4.cpp	i965/vec4: fix splitting of interleaved attributes	2017-11-24 09:24:06 +01:00
brw_vec4.h	intel/compiler: Move the destructor from vec4_visitor to backend_shader	2017-11-07 10:37:52 -08:00
brw_vec4_builder.h
brw_vec4_cmod_propagation.cpp	intel/compiler: Don't propagate cmod into integer multiplies	2017-10-05 11:54:49 -07:00
brw_vec4_copy_propagation.cpp	i965: Support copy propagating of untyped atomic surface indexes.	2017-09-26 15:35:14 -07:00
brw_vec4_cse.cpp
brw_vec4_dead_code_eliminate.cpp	i965/vec4/dce: improve track of partial flag register writes	2017-04-14 14:56:09 -07:00
brw_vec4_generator.cpp	intel: fix disasm_info memory leaks	2017-11-21 08:36:43 +02:00
brw_vec4_gs_nir.cpp	i965/vec4: Delete the system value infastructure	2017-05-09 15:08:07 -07:00
brw_vec4_gs_visitor.cpp	intel/compiler: Remove final_program_size from brw_compile_*	2017-10-31 23:36:54 -07:00
brw_vec4_gs_visitor.h	i965/vec4: Delete the system value infastructure	2017-05-09 15:08:07 -07:00
brw_vec4_live_variables.cpp
brw_vec4_live_variables.h	i965/vec4: consider subregister offset in live variables	2017-04-14 14:56:08 -07:00
brw_vec4_nir.cpp	i965/vec4: use a temp register to compute offsets for pull loads	2017-11-30 07:57:53 +01:00
brw_vec4_reg_allocate.cpp	i965/vec4: Return float from spill_cost_for_type()	2017-08-21 14:45:44 -07:00
brw_vec4_surface_builder.cpp	i965/vec4: Fix swizzles on atomic sources.	2017-09-26 15:35:11 -07:00
brw_vec4_surface_builder.h
brw_vec4_tcs.cpp	intel/compiler: Remove final_program_size from brw_compile_*	2017-10-31 23:36:54 -07:00
brw_vec4_tcs.h	i965/vec4: Delete the system value infastructure	2017-05-09 15:08:07 -07:00
brw_vec4_tes.cpp	i965/vec4: Delete the system value infastructure	2017-05-09 15:08:07 -07:00
brw_vec4_tes.h	i965/vec4: Delete the system value infastructure	2017-05-09 15:08:07 -07:00
brw_vec4_visitor.cpp	i965/vec4: Handle 16-bit types at type_size_xvec4	2017-12-06 08:57:18 +01:00
brw_vec4_vs.h	intel: Rewrite the world of push/pull params	2017-10-12 22:39:29 -07:00
brw_vec4_vs_visitor.cpp	intel/vs: Grow the param array for clip planes	2017-10-12 22:39:30 -07:00
brw_vue_map.c
brw_wm_iz.cpp	nir: Embed the shader_info in the nir_shader again	2017-05-09 15:07:47 -07:00
gen6_gs_visitor.cpp	i965: Move SOL PSIZ hacks from draw time to link time.	2017-06-01 00:08:29 -07:00
gen6_gs_visitor.h
meson.build	i965: Rename intel_asm_annotation -> brw_disasm_info	2017-11-17 12:14:38 -08:00
test_eu_compact.cpp	i965: Remove CONT/BREAK from instruction compaction test	2017-08-21 14:05:23 -07:00
test_eu_validate.cpp	i965: Correct disasm_info usage in eu_validate test	2017-11-18 03:07:06 +02:00
test_fs_cmod_propagation.cpp
test_fs_copy_propagation.cpp
test_fs_saturate_propagation.cpp	i965/fs: Check ADD/MAD with immediates in satprop unit test	2017-11-21 10:13:07 -08:00
test_vec4_cmod_propagation.cpp
test_vec4_copy_propagation.cpp
test_vec4_register_coalesce.cpp
test_vf_float_conversions.cpp