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i965/vec4: Fix swizzles on atomic sources.

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Atomic operation sources are scalar values, but we were failing to
select the .x component of the second operand.  For example,

   atomicCounterCompSwapARB(counter, 5u, 10u)

would generate

   mov(8) vgrf4.x:D, 5D
   mov(8) vgrf5.x:D, 10D

   mov(8) vgrf9.x:UD, vgrf4.xyzw:D
   mov(8) vgrf9.y:UD, vgrf5.xyzw:D

which wrongly selects the .y component of vgrf5, so the actual 10u value
would get dead code eliminated.  The swizzle works for the other source,
but both of them ought to be .xxxx.

Fixes the compare and swap CTS tests in:
KHR-GL45.shader_atomic_counter_ops_tests.ShaderAtomicCounterOpsExchangeTestCase

Cc: "17.2 17.1 17.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Kenneth Graunke 2017-09-24 14:24:53 -07:00
parent a62fe34098
commit 66342c997f
1 changed files with 9 additions and 4 deletions
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13
src/intel/compiler/brw_vec4_surface_builder.cpp
View file

@ -212,10 +212,15 @@ namespace brw {
const unsigned size = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
if (size >= 1)
bld.MOV(writemask(srcs, WRITEMASK_X), src0);
if (size >= 2)
bld.MOV(writemask(srcs, WRITEMASK_Y), src1);
if (size >= 1) {
bld.MOV(writemask(srcs, WRITEMASK_X),
swizzle(src0, BRW_SWIZZLE_XXXX));
}
if (size >= 2) {
bld.MOV(writemask(srcs, WRITEMASK_Y),
swizzle(src1, BRW_SWIZZLE_XXXX));
}
return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC, src_reg(),
emit_insert(bld, addr, dims, has_simd4x2),