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i965/vec4/dce: improve track of partial flag register writes

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This is required for correctness in presence of multiple 4-wide flag
writes (e.g. 4-wide instructions with a conditional mod set) which
update a different portion of the same 8-bit flag subregister.

Right now we keep track of flag dataflow with 8-bit granularity and
consider flag writes to have killed any previous definition of the
same subregister even if the write was less than 8 channels wide,
which can cause live flag register updates to be dead
code-eliminated incorrectly.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Samuel Iglesias Gonsálvez 2017-03-17 11:57:25 +01:00 • committed by Francisco Jerez
parent c1fc8fad47
commit d8441e2276
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_vec4_dead_code_eliminate.cpp
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@ -121,7 +121,7 @@ vec4_visitor::dead_code_eliminate()
}
}
if (inst->writes_flag() && !inst->predicate) {
if (inst->writes_flag() && !inst->predicate && inst->exec_size == 8) {
for (unsigned c = 0; c < 4; c++)
BITSET_CLEAR(flag_live, c);
}