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i965: Add support for control register

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Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.

From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
 subsection "Control Register" (page 754):

"Subregister cr0.0:ud contains normal operation control fields such as the
 floating-point mode ... "

Floating-point Rounding mode is changed at bits 5:4 of cr0.0:

"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
  00b = Round to Nearest or Even (RTNE)
  01b = Round Up, toward +inf (RU)
  10b = Round Down, toward -inf (RD)
  11b = Round Toward Zero (RTZ)"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jose Maria Casanova Crespo 2017-07-01 08:11:58 +02:00
parent 5d5ee507fb
commit ac8d4734f6
1 changed files with 6 additions and 0 deletions
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6
src/intel/compiler/brw_reg.h
View file

@ -816,6 +816,12 @@ brw_notification_reg(void)
WRITEMASK_X);
}
static inline struct brw_reg
brw_cr0_reg(unsigned subnr)
{
return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr);
}
static inline struct brw_reg
brw_sr0_reg(unsigned subnr)
{