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i965/vec4: fix splitting of interleaved attributes

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When we split an instruction that reads an uniform value
(vstride 0) we need to respect the vstride on the second
half of the instruction (that is, the second half should
read the same region as the first).

We were doing this already, but we didn't account for
stages that have interleaved input attributes which also
have a vstride of 0 and need the same treatment.

Fixes the following on Haswell:
KHR-GL45.enhanced_layouts.varying_locations
KHR-GL45.enhanced_layouts.varying_array_locations
KHR-GL45.enhanced_layouts.varying_structure_locations

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Andres Gomez <agomez@igalia.com>
This commit is contained in:
Iago Toral Quiroga 2017-11-21 11:33:53 +01:00
parent 35548cae93
commit f1873956db
1 changed files with 6 additions and 1 deletions
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7
src/intel/compiler/brw_vec4.cpp
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@ -2238,7 +2238,12 @@ vec4_visitor::lower_simd_width()
if (linst->src[i].file == BAD_FILE)
continue;
if (!is_uniform(linst->src[i]))
bool is_interleaved_attr =
linst->src[i].file == ATTR &&
stage_uses_interleaved_attributes(stage,
prog_data->dispatch_mode);
if (!is_uniform(linst->src[i]) && !is_interleaved_attr)
linst->src[i] = horiz_offset(linst->src[i], channel_offset);
}