Samuel Pitoiset 71f5434142 radv: optimize layered fast clear colors when comp-to-single is supported ... comp-to-single is supported since GFX10, it's a new type of DCC fast clear which doesn't require FCE and doesn't require to set fast clear registers (ie. comp-to-reg). This means that it's possible to fast clear even if not all slices are bound, because the clear code is stored in the main image. This improves performance in Dirt Rally 2.0 by +2-5%. Other games that have layered clears would also benefit on GFX10+. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39394>		2026-01-20 18:28:59 +00:00
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addrlib	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
ci	radv/meta: use 2D array for color resolves with compute	2026-01-16 11:35:34 +00:00
common	ac/nir,radv: remove ac_nir_opt_pack_half	2026-01-20 14:48:23 +00:00
compiler	aco/optimizer: apply v_cvt_pkrtz_f16_f32 as fma_mix to operands	2026-01-20 14:48:23 +00:00
drm-shim	amd/drm-shim: add vega20	2026-01-08 09:30:54 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug	2025-12-22 07:34:48 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: add FL capabilitie and lut container size	2025-09-22 10:37:22 +00:00
vulkan	radv: optimize layered fast clear colors when comp-to-single is supported	2026-01-20 18:28:59 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00