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ac/nir,radv: remove ac_nir_opt_pack_half
Foz-DB Navi21: Totals from 2937 (3.01% of 97591) affected shaders: Instrs: 1908695 -> 1908291 (-0.02%); split: -0.02%, +0.00% CodeSize: 10232148 -> 10229224 (-0.03%); split: -0.03%, +0.01% VGPRs: 142168 -> 142080 (-0.06%) Latency: 8052895 -> 8052622 (-0.00%); split: -0.01%, +0.01% InvThroughput: 2550330 -> 2549602 (-0.03%); split: -0.03%, +0.01% VClause: 32601 -> 32603 (+0.01%); split: -0.01%, +0.02% Copies: 118570 -> 118587 (+0.01%); split: -0.04%, +0.05% PreVGPRs: 110090 -> 110082 (-0.01%) VALU: 1468422 -> 1468043 (-0.03%); split: -0.03%, +0.00% SALU: 173858 -> 173828 (-0.02%) Foz-DB Navi48: Totals from 4196 (4.30% of 97637) affected shaders: MaxWaves: 118678 -> 118680 (+0.00%); split: +0.01%, -0.01% Instrs: 3627604 -> 3624093 (-0.10%); split: -0.10%, +0.00% CodeSize: 18956684 -> 18939824 (-0.09%); split: -0.09%, +0.01% VGPRs: 225624 -> 225060 (-0.25%); split: -0.26%, +0.01% Latency: 11856204 -> 11857280 (+0.01%); split: -0.01%, +0.02% InvThroughput: 2388584 -> 2389178 (+0.02%); split: -0.01%, +0.03% VClause: 50409 -> 50410 (+0.00%) SClause: 64701 -> 64699 (-0.00%) Copies: 208353 -> 207522 (-0.40%); split: -0.43%, +0.03% PreVGPRs: 161314 -> 161306 (-0.00%) VALU: 2345604 -> 2345172 (-0.02%); split: -0.02%, +0.00% SALU: 391466 -> 388723 (-0.70%) VOPD: 1788 -> 1806 (+1.01%) Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38815>
This commit is contained in:
Georg Lehmann
Marge Bot
parent
939b4a6476
commit
711598982a
4 changed files with 0 additions and 144 deletions
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@ -130,7 +130,6 @@ amd_common_files = files(
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'nir/ac_nir_meta_cs_blit.c',
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'nir/ac_nir_meta_cs_clear_copy_buffer.c',
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'nir/ac_nir_meta_ps_resolve.c',
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'nir/ac_nir_opt_pack_half.c',
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'nir/ac_nir_opt_shared_append.c',
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'nir/ac_nir_prerast_utils.c',
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'nir/ac_nir_surface.c',
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@ -402,9 +402,6 @@ ac_nir_lower_tex(nir_shader *nir, const ac_nir_lower_tex_options *options);
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void
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ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4);
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bool
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ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level);
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unsigned
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ac_nir_varying_expression_max_cost(nir_shader *producer, nir_shader *consumer);
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@ -1,133 +0,0 @@
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/*
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* Copyright © 2021 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "ac_nir.h"
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#include "ac_nir_helpers.h"
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#include "nir_builder.h"
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static bool
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needs_rounding_mode_16_64(nir_instr *instr)
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{
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if (instr->type != nir_instr_type_alu)
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return false;
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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if (alu->op == nir_op_fquantize2f16)
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return true;
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if (alu->def.bit_size != 16 && alu->def.bit_size != 64)
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return false;
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if (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) != nir_type_float)
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return false;
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switch (alu->op) {
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case nir_op_f2f64:
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case nir_op_b2f64:
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case nir_op_f2f16_rtz:
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case nir_op_b2f16:
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case nir_op_fsat:
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case nir_op_fabs:
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case nir_op_fneg:
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case nir_op_fsign:
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case nir_op_ftrunc:
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case nir_op_fceil:
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case nir_op_ffloor:
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case nir_op_ffract:
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case nir_op_fround_even:
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case nir_op_fmin:
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case nir_op_fmax:
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return false;
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default:
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return true;
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}
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}
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static bool
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can_use_fmamix(nir_scalar s, enum amd_gfx_level gfx_level)
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{
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s = nir_scalar_chase_movs(s);
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if (!list_is_singular(&s.def->uses))
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return false;
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if (nir_scalar_is_intrinsic(s) &&
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nir_scalar_intrinsic_op(s) == nir_intrinsic_load_interpolated_input)
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return gfx_level >= GFX11;
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if (!nir_scalar_is_alu(s))
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return false;
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switch (nir_scalar_alu_op(s)) {
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case nir_op_fmul:
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case nir_op_ffma:
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case nir_op_fadd:
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case nir_op_fsub:
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return true;
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case nir_op_fsat:
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return can_use_fmamix(nir_scalar_chase_alu_src(s, 0), gfx_level);
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default:
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return false;
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}
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}
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static bool
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split_pack_half(nir_builder *b, nir_instr *instr, void *param)
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{
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enum amd_gfx_level gfx_level = *(enum amd_gfx_level *)param;
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if (instr->type != nir_instr_type_alu)
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return false;
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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if (alu->op != nir_op_pack_half_2x16_rtz_split && alu->op != nir_op_pack_half_2x16_split)
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return false;
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nir_scalar s = nir_get_scalar(&alu->def, 0);
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if (!can_use_fmamix(nir_scalar_chase_alu_src(s, 0), gfx_level) ||
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!can_use_fmamix(nir_scalar_chase_alu_src(s, 1), gfx_level))
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return false;
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b->cursor = nir_before_instr(instr);
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b->fp_math_ctrl = alu->fp_math_ctrl;
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/* Split pack_half into two f2f16 to create v_fma_mix{lo,hi}_f16
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* in the backend.
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*/
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nir_def *lo = nir_f2f16(b, nir_ssa_for_alu_src(b, alu, 0));
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nir_def *hi = nir_f2f16(b, nir_ssa_for_alu_src(b, alu, 1));
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nir_def_replace(&alu->def, nir_pack_32_2x16_split(b, lo, hi));
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return true;
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}
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bool
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ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level)
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{
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if (gfx_level < GFX10)
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return false;
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unsigned exec_mode = shader->info.float_controls_execution_mode;
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bool set_mode = false;
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if (!nir_is_rounding_mode_rtz(exec_mode, 16)) {
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nir_foreach_function_impl(impl, shader) {
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nir_foreach_block(block, impl) {
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nir_foreach_instr(instr, block) {
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if (needs_rounding_mode_16_64(instr))
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return false;
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}
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}
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}
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set_mode = true;
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}
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bool progress = nir_shader_instructions_pass(shader, split_pack_half,
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nir_metadata_control_flow,
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&gfx_level);
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if (set_mode && progress) {
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exec_mode &= ~(FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
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exec_mode |= FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64;
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shader->info.float_controls_execution_mode = exec_mode;
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}
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return progress;
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}
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@ -583,13 +583,6 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
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/* cleanup passes */
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NIR_PASS(_, stage->nir, nir_lower_alu_width, ac_nir_opt_vectorize_cb, &gfx_level);
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/* This pass changes the global float control mode to RTZ, so can't be used
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* with LLVM, which only supports RTNE, or RT, where the mode needs to match
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* across separately compiled stages.
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*/
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if (!radv_use_llvm_for_stage(pdev, stage->stage) && !mesa_shader_stage_is_rt(stage->stage))
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NIR_PASS(_, stage->nir, ac_nir_opt_pack_half, gfx_level);
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NIR_PASS(_, stage->nir, nir_lower_load_const_to_scalar);
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NIR_PASS(_, stage->nir, nir_opt_copy_prop);
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NIR_PASS(_, stage->nir, nir_opt_dce);
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