Samuel Pitoiset 3e41b04de9 radv/meta: optimize a barrier with depth/stencil compute resolves ... The compute resolve doesn't use HTILE of the destination image, so the potential HTILE clear can run in parallel. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39805>		2026-02-12 20:17:20 +00:00
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addrlib	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
ci	radv/meta: fix partial depth/stencil resolves with compute	2026-02-12 20:17:18 +00:00
common	ac/vcn_dec: Make the helper functions static	2026-02-12 15:38:26 +00:00
compiler	aco: remove redundant can_use_DPP declaration	2026-02-11 11:34:29 +00:00
drm-shim	amd/drm-shim: add vega20	2026-01-08 09:30:54 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	ac/llvm: remove unpack_half support	2026-02-06 06:12:36 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Adding new wrapper for register profiling	2026-02-12 11:56:26 +00:00
vulkan	radv/meta: optimize a barrier with depth/stencil compute resolves	2026-02-12 20:17:20 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00