HTILE must be decompressed for partial resolves when the hw doesn't
write the decompressed DWORD to HTILE. The driver must also
synchronize the depth/stencil expand if using graphics (the compute
path is already correctly synchronized in the helper).
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39805>
It's not really usefull and only works for H264/5.
On AV1/VP9 it would cause hang.
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39627>
[WHY]
To read back register read/write counts from VPEs, we need to add a new
wrapper function.
[HOW]
Added a wrapper that calls build command and populate the register
profiling data structure.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
The embedded-buffer usage decision should be based on the stream's 3DLUT
mode rather than a loosely defined tm_enabled boolean.
[HOW]
- Replace cmd_info.tm_enabled with cmd_info.lut3d_type
- Add vpe_get_stream_lut3d_type() helper and use it in cmd info/buffer req
- Prefix internal helpers (vpe_calculate_scaling_ratios, vpe_should_generate_cmd_info)
Signed-Off-by: Farhan Rouf <Farhan.Rouf@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[HOW]
- Re-order the function pointer assignments to have the same order as
defined.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-Off-by: Navid Assadian <Navid.Assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
The packet header has uninitialized fields that can introduce 1b'1 in
reserved bits.
[HOW]
initialize the header to 0
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Roy Chan <Roy.Chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Multiplication result may overflow int before it is converted to long
long
[HOW]
Updated the expression to avoid possible overflow
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Support different generations of swizzle mode.
[HOW]
Added different swizzle mode parameters for supporting plane
description.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Ricky Lin <Ricky.Lin@amdeng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Fast load support is required for 3DLUT and Shaper features.
The calculation logic needs to be modularized and exposed via
the resource interface to support this.
[HOW]
1. Add `calculate_shaper` and `program_fastload` function pointers to the `resource` struct.
2. Move shaper normalization, HDR multiplier update, and 3DLUT update logic from
`vpe_color_update_movable_cm` into a new core function `vpe_calculate_shaper`.
3. Implement `vpe10_calculate_shaper` and assign it to the resource function table for VPE10 and VPE11.
4. Update `vpe_create_engine` return signature to remove `const` qualifier.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Reg_update macro and its lastWritten_value design are static global
variables and cannot support multi-thread usage
[HOW]
remove reg_update usage and combine the separated calls together
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
This is necessary for GetPipelineExecutablePropertiesKHR, RADV_DEBUG and
fossil-db.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39827>
pipe_aligned_buffer_create can allow allocate 4GB but that's large enough
for now.
PIPE_USAGE_STREAM is used for now to keep the 2 BOs in GTT.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
Now that we have a solid logic for caching meta objects, trying to
reduce the number of format variants isn't super useful. In practice,
the shaders would be cached on disk, so this would only allocate few
more bytes for the meta objects.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39786>
The Vulkan spec says:
"Store and resolve operations are only performed at the end of a
render pass instance that does not specify the
VK_RENDERING_SUSPENDING_BIT_KHR flag."
VK_RENDERING_SUSPENDING_BIT is also illegal with custom resolves.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
This is mostly for not calling CmdBeginRendering() while rendering
is already active in order to catch potential driver issues. This
requires a small refactoring of how the rendering info is passed for
resolves though.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
Could do better by checking which registers are clobbered/preserved,
but that's unlikely to be useful anyway.
Backport-to: 26.0
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39801>
