Previously, generating inlined function bodies was going to be
difficult, as there was no mapping between the body's declaration of
variables where parameter values were supposed to live and the
parameter variables that a caller would use in paramater setup.
Presumably this also have been a problem for actual codegen.
Making the base e functions IR operations is not a clear win. i965
doesn't support it, it doesn't look like r600 supports it, but r500
does. It should be easily supportable as a lowering pass, though.
Following a discussion in #dri-devel, I think this makes more sense
than implementing it as RSQ RCP CMP as Mesa did. The i965 has a
hardware sqrt that should work, and AMD is suppposed to be able to
implement it as RSQ RCP with an alternate floating point mode so that
the 0.0 case is handled like we want.
