Commit graph

216778 commits

Author SHA1 Message Date
Lionel Landwerlin
9cefd2ddf8 brw: avoid looking at variables to get image formats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36773>
2025-10-07 08:54:26 +00:00
Lionel Landwerlin
96fbca133e iris: run image/intrinsic update pass
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36773>
2025-10-07 08:54:26 +00:00
Lionel Landwerlin
63d3c6379e anv: run image/intrinsic update pass
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36773>
2025-10-07 08:54:26 +00:00
Lionel Landwerlin
94f8d0072d nir: add pass to propagate image format to intrinsics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36773>
2025-10-07 08:54:26 +00:00
Samuel Pitoiset
b8bdc68933 radv/ci: update expected list of failures for VEGA10/NAVI10
Since a8f4a2a9ba ("radv/video: Check FW version before using
WRITE_MEMORY") presumably.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37733>
2025-10-07 08:06:54 +00:00
Martin Roukala (né Peres)
1514a851c8 turnip/ci: enable a750_vk in marge pipelines
The DUTs have been in use for over 2 weeks and the new jobs landed over
1 week ago, without new unknown problems cropping up (not bullet-proof
ethernet gadget).

Additionally, the high temperature (up to 95°C) was discussed with
@lumag and he is not concerned by it... so let's move the jobs to the
merge pipeline!

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37612>
2025-10-07 07:44:35 +00:00
Jesse Natalie
0f1deaa286 dlist: Flush the context during EndList if it's part of a share group and uploaded during recording
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Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37644>
2025-10-06 23:54:09 +00:00
Jesse Natalie
9bab6eb596 wgl: Fix zink depth buffers
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37644>
2025-10-06 23:54:09 +00:00
Caio Oliveira
7b75bf0759 intel/executor: Expose extra command line arguments to script
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37647>
2025-10-06 23:39:37 +00:00
Eric Engestrom
d31f468ad8 Revert "meson: use vcs_tag() instead of custom script"
This reverts commit e4edf9203b.

Meson is unfortunately not quite ready yet, and prints stderr noise when
_not_ building from a git clone.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37717>
2025-10-06 23:06:11 +00:00
Connor Abbott
e5353fd917 tu: Reset *_BIN_FOVEAT when not using FDM
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Don't let old values from a previous renderpass through.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37723>
2025-10-06 22:42:32 +00:00
Lionel Landwerlin
f8cbc558db vulkan/render_pass: fixup renderpasses barriers for 2D views of 3D images
With maintenance9 enabled

Spec clarification : https://gitlab.khronos.org/vulkan/vulkan/-/merge_requests/7629

Fixes: 595889018a ("anv: implement VK_KHR_maintenance9")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13669
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36624>
2025-10-06 22:20:26 +00:00
Juan A. Suarez Romero
d775f3b608 ci: uprev VKCTS to 1.4.3.3
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37620>
2025-10-06 21:53:39 +00:00
Benjamin Cheng
364a2488ad radv/video: Report extra image usages
ENCODE_SRC and DECODE_DST are transparent and can have additional
usages.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37656>
2025-10-06 21:27:48 +00:00
Benjamin Cheng
d1872c45ae radv/video: Fix video profile reporting
Use vk_video_is_profile_supported first, and add AMD specific
restrictions later.

vulkaninfo reports on Navi31:
    H.264 Decode (4:2:0 8-bit) Baseline progressive
    H.264 Decode (4:2:0 8-bit) Main progressive
    H.264 Decode (4:2:0 8-bit) High progressive
    H.264 Decode (4:2:0 8-bit) Baseline interlaced (interleaved lines)
    H.264 Decode (4:2:0 8-bit) Main interlaced (interleaved lines)
    H.264 Decode (4:2:0 8-bit) High interlaced (interleaved lines)
    H.264 Decode (monochrome 8-bit) High progressive
    H.264 Decode (monochrome 8-bit) High interlaced (interleaved lines)
    H.265 Decode (4:2:0 8-bit) Main
    H.265 Decode (4:2:0 8-bit) Main 10
    H.265 Decode (4:2:0 8-bit) Main Still Picture
    H.265 Decode (4:2:0 10-bit) Main 10
    VP9 Decode (4:2:0 8-bit) Profile 0
    VP9 Decode (4:2:0 10-bit) Profile 2
    AV1 Decode (4:2:0 8-bit) Main with film grain support
    AV1 Decode (4:2:0 8-bit) Main without film grain support
    AV1 Decode (4:2:0 10-bit) Main with film grain support
    AV1 Decode (4:2:0 10-bit) Main without film grain support
    AV1 Decode (4:2:0 12-bit) Professional with film grain support
    AV1 Decode (4:2:0 12-bit) Professional without film grain support
    AV1 Decode (monochrome 8-bit) Main with film grain support
    AV1 Decode (monochrome 8-bit) Main without film grain support
    AV1 Decode (monochrome 10-bit) Main with film grain support
    AV1 Decode (monochrome 10-bit) Main without film grain support
    AV1 Decode (monochrome 12-bit) Professional with film grain support
    AV1 Decode (monochrome 12-bit) Professional without film grain support
    H.264 Encode (4:2:0 8-bit) Baseline
    H.264 Encode (4:2:0 8-bit) Main
    H.264 Encode (4:2:0 8-bit) High
    H.265 Encode (4:2:0 8-bit) Main
    H.265 Encode (4:2:0 8-bit) Main 10
    H.265 Encode (4:2:0 8-bit) Main Still Picture
    H.265 Encode (4:2:0 10-bit) Main 10
    AV1 Encode (4:2:0 8-bit) Main
    AV1 Encode (4:2:0 10-bit) Main

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37656>
2025-10-06 21:27:48 +00:00
Benjamin Cheng
5e297c7444 vulkan/video: Add vk_video_is_profile_supported()
This helper sanity-checks a VkVideoProfileInfoKHR to make sure it
represents a real profile corresponding to specific codec rules.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37656>
2025-10-06 21:27:47 +00:00
Mike Blumenkrantz
e12d019b9d zink: various fixes for custom sample locations
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this is still not technically correct, as I'm seeing some weird fails
on ANV, at least, and also it maybe needs a pass to strip InterpolateAtSample
(related?), but it is now actually enabling custom sample locations

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37618>
2025-10-06 19:51:44 +00:00
Ian Romanick
911f033058 elk: Set lower_txd_data to devinfo
Otherwise data will be NULL, and there will be an instant segfault.

Closes: #14035
Fixes: a49cf90e14 ("elk: use the new lower_txd_cb")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37698>
2025-10-06 19:24:34 +00:00
Rob Clark
e60d34fa78 freedreno: Disable explicit sync heuristic for Xwayland
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Xwayland seems to mix implicit and explicit sync, depending on client
app.  This trips up the heuristic that disables implicit sync once it
starts seeing app using explicit sync.  This is not typical behavior,
so add a driconf override to disable the heuristic.

Fixes: 137cd3b0fa ("freedreno/drm: Move no_implicit_sync accounting")
Cc: mesa-stable
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37703>
2025-10-06 15:55:48 +00:00
Aitor Camacho
f21d0f2cbe meson: static link spirv-tools for darwin
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37495>
2025-10-06 15:19:55 +00:00
Valentine Burley
7267791292 ci/android: Upload arm64 Mesa driver builds
Save the arm64 driver builds in a separate archive alongside the x86_64
ones.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37596>
2025-10-06 14:46:22 +00:00
Nanley Chery
53838f596b iris: Drop iris_resource_level_has_hiz()
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This function disabled HiZ support when it encountered LODs which did
not satisfy a restriction of ISL_AUX_OP_AMBIGUATE for gfx8-9. Now that
the previous commit avoids that auxiliary operation for those platforms,
it is not so useful. Replace it with a simple check of the aux-usage.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:41 +00:00
Nanley Chery
a098077366 iris: Initialize HiZ to the CLEAR state on BDW-ICL
We disable HiZ for some LODs on gfx8-9 to comply with ambiguate
operation restrictions. Avoid this restriction by initializing HiZ to
the CLEAR state on those platforms. By doing this, an ambiguate will
never occur. Also, do this for ICL as an optimization.

We'll enable HiZ for all LODs on gfx8-9 in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:39 +00:00
Nanley Chery
5964c31429 iris: Don't zero the CCS in an already zeroed BO
Avoid redundant work. Includes a refactor that will be helpful for HiZ
in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:39 +00:00
Nanley Chery
ef4f4d3f84 intel/isl: Update the aux-state of zeroed HiZ
By dumping the contents of a HiZ buffer before and after fast-clearing,
I've observed that a zeroed HiZ block corresponds to the CLEAR state
until gfx12. The fast-clearing application was piglit's bin/hiz. I ran
this test on a couple bare metal platforms (ICL and BDW) and many
simulated ones (SKL, TGL, DG2, and LNL).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:39 +00:00
Nanley Chery
a13aab1859 intel/isl: Update the initial HiZ state for Xe2+
Avoids ambiguating in iris and anv.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:39 +00:00
Nanley Chery
b709d7dd39 intel: Delete the has_illegal_ccs_values bool
This was only used in one location.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:39 +00:00
Nanley Chery
d41bff3836 anv: Query ISL for the aux-state of undefined layouts
For CCS_E on gfx12+, this will cause us to perform full resolves when
transitioning from undefined to a layout which does not support
compression. We don't currently perform such transitions because
compression is always enabled.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:38 +00:00
Nanley Chery
7d284fe399 intel/isl: Define initial state of non-zeroed CCS on gfx9-11
isl_aux_get_initial_state() will soon be used for non-zeroed CCS on
gfx9+. Update the function to avoid hitting an unreachable().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:37 +00:00
Lionel Landwerlin
69771e4bfe brw: fix render target indexing in FS output reads
I forgot that the base indice is actually a more complex value that
encodes the render target index and other things.

Also fix the 1d-layered accesses by checking the size of the
framebuffer.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14008
Fixes: d4ab2087cf ("brw: lower non coherent FS load_output in NIR")
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37653>
2025-10-06 13:24:16 +00:00
Zan Dobersek
27c16c46fd fd: allow limiting RD dumps to specific frames and submits
RD dump generation can be expensive and can only be desired for some
specific part of execution. Trigger file mechanism helps with this to a
certain degree but is still somewhat inexact.

FD_RD_DUMP_SUBMITS environment variable can be used to specify ranges of
submit indices for which RD dumps of command streams should be generated.
FD_RD_DUMP_FRAMES environment variable can similarly be used to specify
ranges of frames under which RD dumps for submitted command streams should
be generated. Frame ranges only really work with Turnip since the frame
count data is available there.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37499>
2025-10-06 12:07:55 +00:00
Sergi Blanch Torne
19b3237408 Revert "ci: disable Collabora's farm due to maintenance"
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This reverts commit 4e8f01b864.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37712>
2025-10-06 13:00:52 +02:00
David Rosca
59a3ca2333 radv/video: Fix waiting on encode feedback query
Currently we wait until the second dword in feedback buffer changes
from 0 to 1, and then the rest of the feedback is read. There is no
guarantee that the rest of the feedback will be available, which can
cause bitstream size to be incorrectly returned as 0.

Add write memory command after encode, marking the query as available
to ensure the entire feedback buffer is ready.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13601
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36772>
2025-10-06 10:32:54 +00:00
David Rosca
a8f4a2a9ba radv/video: Check FW version before using WRITE_MEMORY
Move the version check to separate function so that it can
also be used elsewhere.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36772>
2025-10-06 10:32:54 +00:00
David Rosca
40c124e67a radv: Change radv_vcn_write_event to a write memory func
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36772>
2025-10-06 10:32:53 +00:00
Eric Engestrom
2ecd354a22 ci: check for missing meson dependencies
Based on @eschwartz's https://codeberg.org/eli-schwartz/eschwartz-dev-scripts/src/branch/master/install-qa-check.d/50ninja-missingdeps

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37490>
2025-10-06 09:53:24 +00:00
Eric Engestrom
e17469f99f ci/alpine: install the real ninja package
The `samurai` re-implementation that we'd been using is missing the
tools, in particular `missingdeps` which we're about to start using, so
let's not leave alpine out.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37490>
2025-10-06 09:53:24 +00:00
Eric Engestrom
3f40a7d998 docs: finish converting the docs job into a meson build job
This is required for the next job, because we'll need a login shell
session to be able to use `ninja`, which the normal build jobs
automatically handle, but the custom docs job we had didn't.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37490>
2025-10-06 09:53:24 +00:00
Eric Engestrom
43eb5555df iris/meson: generate git_sha1.h before compiling iris_program.c
Fixes: dedbe0e826 ("iris: Create archive file when using INTEL_DEBUG=mda")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37490>
2025-10-06 09:53:24 +00:00
Sergi Blanch Torne
cf9b0c1fd3 ci: fix requirements file
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With the migration concluded on !37510 of the lava-job-submitter (it is now an
independent project under the gfx-ci namespace), a lava requirements file was
not necessary anymore, but there was still one reference.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37713>
2025-10-06 09:18:49 +00:00
Erik Faye-Lund
478e8f11c4 pvr: split out rogue hw-defs to separate folder
This just carves out some space for future architectures in the source
tree.

Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37675>
2025-10-06 11:02:04 +02:00
Erik Faye-Lund
88e626b6eb pvr: kill rogue_hwdefs.h
This header is only used in a single place, which will generate macros
based on these definitions. Let's remove the header, and just include
the separate files in pvr_csb.h instead.

Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37675>
2025-10-06 11:02:00 +02:00
Erik Faye-Lund
be0c740c73 pvr: include pvr_csb.h first in implementation
This just makes sure the header file is free-standing.

Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37675>
2025-10-06 11:01:28 +02:00
Frank Binns
162cc070f0 docs: add pvr VK 1.0, extensions and optional features to new_features.txt
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Simon Perretta <simon.perretta@imgtec.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37683>
2025-10-06 08:09:34 +00:00
David Rosca
af79dd205e pipe: Remove resource_get_info
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Not used anymore.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37628>
2025-10-06 07:11:09 +00:00
David Rosca
b25c40b857 frontends/va: Use resource_get_param instead of resource_get_info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37628>
2025-10-06 07:11:09 +00:00
David Rosca
25de079408 d3d12: Implement resource_get_param
Reviewed-By: Silvio Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37628>
2025-10-06 07:11:09 +00:00
David Rosca
02aaf360ae r600: Implement resource_get_param
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37628>
2025-10-06 07:11:09 +00:00
Samuel Pitoiset
874bc09537 radv: reserve more CS space when executing DGC calls
This can trigger an assert otherwise. The space reserved before
executing DGC IBs is an arbitrary number which should be large enough
in all cases.

Found this while implementing descriptor heap.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37681>
2025-10-06 06:28:18 +00:00
Sergi Blanch Torne
4e8f01b864 ci: disable Collabora's farm due to maintenance
Planned downtime in the farm:
* Start: 2025-10-06 07:00 UTC
* End: 2025-10-06 13:00 UTC

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37431>
2025-10-06 06:02:59 +00:00