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radv: reserve more CS space when executing DGC calls

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This can trigger an assert otherwise. The space reserved before
executing DGC IBs is an arbitrary number which should be large enough
in all cases.

Found this while implementing descriptor heap.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37681>
This commit is contained in:
Samuel Pitoiset 2025-10-03 11:28:13 +02:00 • committed by Marge Bot
parent 4e8f01b864
commit 874bc09537
1 changed files with 4 additions and 0 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
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@ -12897,6 +12897,8 @@ radv_dgc_execute_ib(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommand
const uint64_t main_trailer_va = ib_va + radv_get_indirect_main_trailer_offset(pGeneratedCommandsInfo);
struct radv_cmd_stream *cs = cmd_buffer->cs;
radeon_check_space(device->ws, cs->b, 64);
device->ws->cs_chain_dgc_ib(cs->b, main_ib_va, cmdbuf_size >> 2, main_trailer_va, cmd_buffer->state.predicating);
if (task_shader) {
@ -13012,6 +13014,8 @@ radv_CmdExecuteGeneratedCommandsEXT(VkCommandBuffer commandBuffer, VkBool32 isPr
}
if (!radv_cmd_buffer_uses_mec(cmd_buffer)) {
radeon_check_space(device->ws, cs->b, 2);
radeon_begin(cs);
radeon_emit(PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
radeon_emit(0);