Commit graph

223615 commits

Author SHA1 Message Date
Erik Faye-Lund
fbfd5be469 pan/ci: reenable passing tests
These tests pass, so let's remove their skips and xfails.

The immediate-reuse failures seems to actually be flaky.

Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40398>
2026-06-03 12:14:06 +00:00
Erik Faye-Lund
d093caffcf pan/ci: stuff some breadcrumbs in the fails-list
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40398>
2026-06-03 12:14:06 +00:00
Erik Faye-Lund
06a05e58e0 pan/ci: move cts-bug-fails to skips
These are known fails due to CTS bugs. Patches are on the way. Let's
skip them, like we do with the other ones in the same category.

Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40398>
2026-06-03 12:14:06 +00:00
Erik Faye-Lund
d4778fd610 pan/ci: use slow-skips to only skip slow tests for merge-requests
Slow tests are less of a problem on nightly runs, so let's switch to the
slow-skips.txt files here.

Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40398>
2026-06-03 12:14:06 +00:00
Nick Hamilton
46853bff63 pvr: Fix load-op shader when loading from a 2d image view of a 3d image
When zink translates glCopySubImageData with a 2d image view of a 3d
image as the destination to a draw call the shader generated for the
load-op was not handling things correctly leading to the wrong
z-slice been loaded.

The fix is to mark which attachments within the load op are 2d image
views of a 3d image then when generating the load-op shader covert
the sample to 3d sample and update the coords to load the required
z-slice value from the tex meta data.

Fix for dEQP-GLES31.functional.copy_image.non_compressed.*_to_texture3d

Fixes: 7b28b6c43d ("pvr, pco: implement VK_EXT_image_2d_view_of_3d")

Signed-off-by: Nick Hamilton <nick.hamilton@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41955>
2026-06-03 11:12:42 +00:00
Collabora's Gfx CI Team
b2eeef663b Uprev VVL to d2b091858d12802cc1c3722c81a9f3d865d833d4
Some checks are pending
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315d28985e...d2b091858d

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41948>
2026-06-03 10:44:57 +00:00
Eric Engestrom
3808c7c60b docs: add sha sum for 26.1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41989>
2026-06-03 10:39:06 +00:00
Eric Engestrom
31416000b0 docs: add release notes for 26.1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41989>
2026-06-03 10:39:06 +00:00
Eric Engestrom
d32241f6c2 docs: update calendar for 26.1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41989>
2026-06-03 10:39:06 +00:00
Thong Thai
90f505b763 radeonsi: Allow call to stub'd si_init_gfx_context to continue
With a decode-only build, the si_init_gfx_context is stubbed and returns
false, which causes si_create_context to fail when a decoder is created
(since si_dec_init_decode sets the PIPE_CONTEXT_COMPUTE_ONLY flag).

With this change, the stubbed si_init_gfx_context function returns true,
which allows si_create_context to continue, and a decoder to be
successfully created.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41973>
2026-06-03 09:56:20 +00:00
Thong Thai
6f184aae8a meson: Don't require libelf for radeonsi when with_gfx_compute is false
Since shader support is not built when with_gfx_compute is false, libelf
is not needed.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41973>
2026-06-03 09:56:19 +00:00
Marc Alcala Prieto
0998c81058 pan/csf: Fix incremental rendering on v14+
The fragment state is stored just before ZS_CRC_EXTENSION, so move the
pointer accordingly.

Fixes: af35fc44a7 ("pan/desc: Implement pan_emit_fbd for v14+")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41643>
2026-06-03 08:47:42 +00:00
Marc Alcala Prieto
0359a756c4 panvk/csf: Implement incremental rendering on v14+
Implement the v14+ paths needed to copy IR framebuffer layer state and
re-emit it from the tiler OOM exception handler.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41643>
2026-06-03 08:47:42 +00:00
Marc Alcala Prieto
588e211fde panvk/csf: Emit fragment layer state just before RUN_FRAGMENT2
Postpone emitting the fragment layer state in the fragment job issue path
until just before RUN_FRAGMENT2 is emitted.

This state is loaded from FBD_POINTER which might change due to IR.
Therefore, postponing is required.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41643>
2026-06-03 08:47:42 +00:00
Marc Alcala Prieto
5a7159f869 panfrost: Remove duplicated flushes before RUN_FRAGMENT[2]
The cs_builder.h helper that records RUN_FRAGMENT[2] also records a flush,
so there's no need for flushing again before calling it.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41643>
2026-06-03 08:47:42 +00:00
Samuel Pitoiset
cdac2d65b3 radv: return VK_ERROR_INITIALIZATION_FAILED if VM_ALWAYS_VALID isn't supported
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Better than asserting.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41960>
2026-06-03 08:22:39 +00:00
Samuel Pitoiset
16153e3f69 radv: cleanup occurrences of radeon_info::has_vm_always_valid
It must be supported and there is already an assertion in
radv_CreateDevice().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41960>
2026-06-03 08:22:39 +00:00
Samuel Pitoiset
52176d43c0 radv/amdgpu: allow RADV_PERFTEST=localbos with virtio
VM_ALWAYS_VALID should be supported now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41960>
2026-06-03 08:22:39 +00:00
Valentine Burley
879dd9ca8c tu: Advertise VK_KHR_internally_synchronized_queues
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This is implemented in common code in d8ef386f98 ("vulkan: add support
for VK_KHR_internally_synchronized_queues").

Passes dEQP-VK.synchronization2.internally_synchronized_queues.*

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41926>
2026-06-03 06:21:30 +00:00
Olivia Lee
f1c30d65e1 pan/v13: implement CS udiv
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This will be used for CmdDrawByteCountIndirect on v13, which requires
dividing the byte count by the vertex stride to get the number of
vertices in the draw.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
2026-06-03 01:12:23 +00:00
Olivia Lee
ab34d3af23 pan/v13: implement constant integer multiplication CS helper
All we really need for udiv32 is a 32x32->64 multiply, but the most
efficient way to implement that is to move the 32-bit reg into a 64-bit
reg anyway. So, I figured it simpler to just have the caller do that
than passing a scratch reg into the helper.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
2026-06-03 01:12:23 +00:00
Olivia Lee
d505009ef0 pan/v13: add CS builder functions for shift instructions
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
2026-06-03 01:12:23 +00:00
Olivia Lee
9d90d33776 pan/v13: add CS builder functions for reg/reg add and sub instructions
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
2026-06-03 01:12:23 +00:00
Olivia Lee
b4ae8e548f pan/csf: rename immediate CS add builder functions
v13 adds some register add/sub instructions, and I'd like to use
cs_{add,sub}{32,64} for those to match the naming convention for other
reg/reg instructions. So the existing immediate functions are renamed to
cs_add_imm{32,64}, matching the name of the actual instruction.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
2026-06-03 01:12:23 +00:00
Nanley Chery
2581ae572b anv: Allow partial depth fast clears on gfx12+
Not sure if any workload uses this. This mostly allows us to document
the functionality of HSD 22011236099 on gfx20+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
2026-06-03 00:51:29 +00:00
Nanley Chery
6f7baf4e7d anv: Skip some CCS performance warnings on gfx9-11
These platforms don't support CCS on MCS/HIZ/STC. There's nothing we can
do about this. So, stop warning about it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
2026-06-03 00:51:28 +00:00
Nanley Chery
888ea50760 anv: Dedent a closing curly brace
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
2026-06-03 00:51:28 +00:00
Nanley Chery
ee40162321 intel/isl: Fix the initial state HiZ state for Xe2+
HSD 22011236099 actually states that there are no illegal values for HiZ
for partial clear operations. Other operations (e.g., copies) may still
result in corruption without a preceding ambiguate.

Fixes: a13aab1859 ("intel/isl: Update the initial HiZ state for Xe2+")
Related: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40987
Tested-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
2026-06-03 00:51:27 +00:00
Caio Oliveira
94fc269270 jay: Add INTEL_DEBUG=mda support
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41897>
2026-06-03 00:24:49 +00:00
Caio Oliveira
6701351645 jay: Unify macro for NIR passes
This is a preparation for enabling INTEL_DEBUG=mda in Jay.  Since we are
changing the passes to use a new macro, go ahead and use new JAY_NIR_*
macros so we don't have to rename them again when their implementation
gets decoupled from BRW.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41897>
2026-06-03 00:24:49 +00:00
Yiwei Zhang
bff4e7e4c1 tu: fix to report device memory with heapIndex
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The report data requires VkDeviceMemoryReportCallbackDataEXT::heapIndex
instead of memory type index. Meanwhile, turnip only supports a single
tu_memory_heap and doesn't have a type-to-heap mapping. So here we fix
to report constant 0 for heapIndex.

Fixes: 6d69d7e6bf ("tu: Implement VK_EXT_device_memory_report")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41974>
2026-06-02 23:53:48 +00:00
Yiwei Zhang
02fd326b4a panvk: fix to report device memory with heapIndex
The report data requires VkDeviceMemoryReportCallbackDataEXT::heapIndex
instead of memory type index.

Fixes: c6ff8ce373 ("panvk: support VK_EXT_device_memory_report")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41974>
2026-06-02 23:53:48 +00:00
Mel Henning
e68c9b791c compiler/rust: Fix inline wrapper include dir
This follows the same pattern rusticl uses to handle this. See 36a18208f7

Fixes: b60694b91e ("compiler/rust: Add a float16 wrapper")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15586
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41964>
2026-06-02 22:53:26 +00:00
Daivik Bhatia
990d76eae6 v3dv: Implement and enable nullDescriptor support
Handle null descriptors by emitting zeroed descriptor state.
When the nullDescriptor feature is enabled, a dedicated null_bo is
allocated. Null image descriptors now pack a TEXTURE_SHADER_STATE whose
base address points to this BO, ensuring that the TMU reads from valid
memory.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40485>
2026-06-02 22:29:00 +00:00
Daivik Bhatia
6aed7d2988 broadcom/compiler: add support for null descriptors
Add `v3d_nir_lower_null_descriptors` NIR pass to bypass operations
if the descriptor size is zero, returning 0 where necessary.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40485>
2026-06-02 22:29:00 +00:00
Paulo Zanoni
a268f79ce1 intel/tools: fix stall_csv_filename maybe-unitialized error
On Release builds, I get this:

../../src/intel/tools/intel_eu_stall_viewer.cpp: In function ‘int main(int, char**)’:
../../src/intel/tools/intel_eu_stall_viewer.cpp:269:27: warning: ‘stall_csv_filename’ may be used uninitialized [-Wmaybe-uninitialized]
  269 |    if (!shaders_directory || !stall_csv_filename) {
      |        ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~
../../src/intel/tools/intel_eu_stall_viewer.cpp:244:43: note: ‘stall_csv_filename’ was declared here
  244 |    const char *shaders_directory = NULL, *stall_csv_filename;

We can't expect gcc to understand that it's a required argument.

This "fixes" b795a1a20c ("intel/tools: add eu stall viewer").

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41946>
2026-06-02 22:01:01 +00:00
Faith Ekstrand
84e29bbdc2 kraid: Box ops inside Op
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We found this to be a good balanc in NAK.  Instr itself is inlined and
so is the op discriminant but the contents of the op is boxed.  This
means we can determine what op something is without chasing a pointer
but still get to mostly copy pointers as we modify instruction lists.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
c64e968bf8 kraid/isa: Handle field restrictions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
6f214056ce kraid: Add a Model::op_src_supports_imm32() query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
6cf32abe6b kraid: Make Instruction::get_info() more ergonamic
Since it's returning an Option<&InstructionInfo> anyway, we can handle
the try_into() on behalf of the caller.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
8a2160c611 kraid: Implement nir_op_f2f*
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
ef16712025 kraid: Map H01 and B0123 to None in the encoder
These are an annoying special case.  In order to keep things consistent
and let us pass in None when we don't want any swizzling and ensure that
None both means "Don't swizzle because this instruction can't" and the
identity swizzle, we need to pick a canonical form.  We're already using
None for missing values so it makes sense to canonicalize to None.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
b4947b2a14 kraid: Be more lax about immediates
Instead of asserting that the swizzle replicates, look at the actual
value we're swizzling.  This lets us get away with putting immediates
in 8 and 16-bit ops in more cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
0c51b7ffe9 kraid: Implement nir_op_extract_*
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
aa766b8f76 kraid: Add a 16-bit ALU lowering pass
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
b56bf05075 kraid: Add a SrcRef::Zero
While special constants may, in theory, depend on the hardware
generation, we're always guaranteed a free constant zero.  It's
convenient to have this at a higher level in the IR.  Zeros also
don't count towards FAU and special constant read limits so there's
no real risk in special-casing them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
ebe91b02c4 kraid: Implement nir_op_u2u/i2i
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
cd679dbc5d kraid: Support signless IAdd
Signed and unsigned types are only allowed for IADD and not IADD_IMM so
it's simpler if we support signless for regular IADD.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
1ad7ddf076 kraid: Claim we use 64 registers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00
Faith Ekstrand
f6ed151807 kraid: Implement OpCSel and nir_op_[ui]min/max
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
2026-06-02 21:19:27 +00:00