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Author SHA1 Message Date
David Rosca
f9c646670b radeonsi/video: Don't report support for H264 Baseline profile 
Frontend was using PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE for
VAProfileH264ConstrainedBaseline, so this hasn't caused any issues.
Change it to correct enum value to make it less confusing.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38748>
 2026-01-12 11:21:39 +00:00
David Rosca
6ed00e2d5d frontends/va: Use correct pipe profile for VAProfileH264ConstrainedBaseline 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38748>
 2026-01-12 11:21:39 +00:00
David Rosca
0518784b62 radv/amdgpu: Only wait on queue syncobj when needed 
This would always wait on the queue syncobj if there was any other
wait syncobj, but it should only wait after zero submit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39193>
 2026-01-12 10:59:03 +00:00
Dave Airlie
ab9e904f24 radv/coopmat: fix deref stride
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This at least fixes the nir debug output to have correct values.

Fixes: 48fc8c8d1c ("radv/nir/lower_cmat: set optimal load/store alignment")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39256>
 2026-01-12 10:39:05 +00:00
David Rosca
df4220d500 radv/video: Use different dpb swizzle mode for 10 bit encode 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39189>
 2026-01-12 10:18:18 +00:00
David Rosca
587a7aa510 radv: Enable DCC modifiers for multi plane formats on GFX12 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39190>
 2026-01-12 09:57:56 +00:00
Samuel Pitoiset
5bcca4a832 radv/spm: use a staging buffer for faster reads on dGPUS 
This allows us to move the SPM buffer to VRAM because I think it must
be in VRAM too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:37 +00:00
Samuel Pitoiset
6863a90486 radv/spm: rework allocating the SPM buffer 
For using a staging buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:37 +00:00
Samuel Pitoiset
c7d0aa6671 radv/sqtt: use a staging buffer for faster reads on dGPUS 
This is way faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:36 +00:00
Samuel Pitoiset
5d430940d2 radv/sqtt: rework allocating the SQTT buffer 
For using a staging buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:36 +00:00
Samuel Pitoiset
1c611c2dac radv/sqtt: use VkCommandBuffer objects for SQTT start/stop sequences 
For using a staging buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:35 +00:00
Marek Olšák
ceb2667cf3 gallium/util: print task/mesh statistics in util_end_pipestat_query 
Used for debugging. Not used by anything in the tree.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39253>
 2026-01-12 08:51:15 +00:00
Yiwei Zhang
b41f466045 panvk: fix to defer disk cache init after vk_physical_device_init
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Instead of initializing the disk cache earlier, the vk_properties
filling can be deferred after disk cache init is done. Otherwise, the
created disk cache will be zero'ed out in vk_physical_device_init,
ending up with leaked alloc and disabled disk cache (though advertised).

Fixes: acd00c07f6 ("panvk: Initialize the disk cache earlier")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39248>
 2026-01-12 08:34:46 +00:00
Samuel Pitoiset
6f4b3c7c9b ac/perfcounter: re-order GPU perf blocks on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
653b39989a ac/perfcounter: define more GPU blocks on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
d391cd0c4d ac/perfcounter: fix number of scoped instances for RMI block 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
ea63aa3e8e ac/perfcounter: add missing configuration for GCEA on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
6722a6332a ac,radv,radeonsi: rename num_spm_counters to num_spm_modules 
A module can have different number of counters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:32 +00:00
Samuel Pitoiset
fb43d7bff2 ac/perfcounter: re-order GPU perf blocks on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:31 +00:00
Samuel Pitoiset
3b6ff80d48 ac/perfcounter: define more GPU blocks on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:31 +00:00
Samuel Pitoiset
eb37d6ceb7 ac/perfcounter: fix computing number of 16-bit/32-bit SPM counters 
Determine them only when both are explicitly 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:30 +00:00
Samuel Pitoiset
d1efdc7e76 ac/perfcounter: fix number of 32-bit SPM counters 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:29 +00:00
Samuel Pitoiset
9fe57d3882 ac/spm: define new per-shader engine blocks 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:29 +00:00
Samuel Pitoiset
60fac38491 ac/spm: fix typo in one GPU perf block name 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:29 +00:00
Samuel Pitoiset
db02077c8a radv: remove extra instructions after UNREACHABLE 
Minor cleanups.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39237>
 2026-01-12 07:41:08 +00:00
Samuel Pitoiset
e1e2517664 radv: use UNREACHABLE for illegal texture filter 
Found this with a broken CTS test, way easier to crash for isolating
the test case.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39237>
 2026-01-12 07:41:08 +00:00
Samuel Pitoiset
91e0f8f1e5 radv/rt: fix a compilation warning about uninitialized fields 
Just zero-initialize the layout struct to fix the following warning
because radv_use_bvh8() might return FALSE.

../src/amd/vulkan/radv_acceleration_structure.c: In function ‘radv_update_as_gfx12’:
../src/amd/vulkan/radv_acceleration_structure.c:873:70: warning: ‘layout.bounds_offsets’ may be used uninitialized [-Wmaybe-uninitialized]
  873 |       .bounds = state->build_info->scratchData.deviceAddress + layout.bounds_offsets,
      |                                                                ~~~~~~^~~~~~~~~~~~~~~
../src/amd/vulkan/radv_acceleration_structure.c:866:33: note: ‘layout.bounds_offsets’ was declared here
  866 |    struct update_scratch_layout layout;
      |                                 ^~~~~~

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39228>
 2026-01-12 07:18:50 +00:00
Sergi Blanch Torne
548e195eb4 ci: disable Collabora's farm due to maintenance 
Planned downtime in the farm:
* Start: 2026-01-12 08:00 UTC
* End: 2026-01-12 16:00 UTC

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39044>
 2026-01-12 07:02:30 +00:00
Dave Airlie
b4023532e3 lavapipe: drop unused defines
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Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39255>
 2026-01-11 20:48:01 +00:00
Dave Airlie
a82c68c439 lavapipe: drop data pointer from lvp_query 
There is no need to store this.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39255>
 2026-01-11 20:48:01 +00:00
Dave Airlie
6d9ad83f8f lavapipe: drop mem pointer and offset from buffer 
these aren't used.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39255>
 2026-01-11 20:48:01 +00:00
Dave Airlie
8b512692f5 lavapipe: repack render attachment. 
just a trivial repack

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39255>
 2026-01-11 20:48:01 +00:00
Dave Airlie
e21d1bcea7 lavapipe: drop apiVersion from instance 
this isn't used

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39255>
 2026-01-11 20:48:01 +00:00
Mary Guillemard
9a6c57b5c7 hk: Hash the multiview mask for both vertex and fragment stages
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We were only accounting for the multiview mask when the fragment stage
was present causing wrong cached shaders to be possibly used.

This fixes
"dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.*_multiview"
failures.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39238>
 2026-01-10 17:42:26 +00:00
Alyssa Ross
f677b3eb48 rocket: fix building for musl 
musl follows POSIX and provides ioctl as int ioctl(int, int, ...).

Fixes: 5b829658f7 ("rocket: Initial commit occf a driver for Rockchip's NPU")
Signed-off-by: Alyssa Ross <hi@alyssa.is>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38561>
 2026-01-10 16:01:55 +00:00
Maíra Canal
df85401e8e docs/teflon: Update documentation with more recent output
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Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38942>
 2026-01-10 14:05:48 +00:00
Maíra Canal
9bf0ad3b15 docs/envvars: Document Teflon environment variables 
Add documentation describing the use of Teflon's environment variables.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38942>
 2026-01-10 14:05:48 +00:00
Maíra Canal
7308ebd9cd teflon: List all supported operations on tflite_builtin_op_name() 
When running ``Models.Op/yolox_114`` on Etnaviv with TEFLON_DEBUG=verbose,
the delegate currently reports supported operations as unknown, for example:

Teflon delegate: loaded etnaviv driver
idx    type ver support     inputs
=================================================================
  0 unknown v2  supported   in: 0(i8) 1(i32) out: 2(i8)

This happens because not all operations supported by Teflon are mapped
in ``tflite_builtin_op_name()``. Therefore, extend ``tflite_builtin_op_name()``
to include all operations supported, ensuring that the operation type
is reported correctly during debug.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38942>
 2026-01-10 14:05:48 +00:00
Maíra Canal
104d1a0d4b teflon: Improve dumped graph formatting 
Currently, the graph dumped with ``TEFLON_DEBUG=verbose`` has the
following appearance:

idx type                      inputs                   outputs  operation type-specific
================================================================================================
  0 CONV   88,8,6 7
  1 DWCONV 7,35,34 33
  2 CONV   33,38,36 37
  3 DWCONV 37,41,40 39
  [...]
 20 CONV   9,14,12 13
 21 DWCONV 13,17,16 15
 22 CONV   15,20,18 19
 23 DWCONV 19,23,22 21
 24 CONV   21,26,24 25
 25 DWCONV 25,29,28 27
 26 CONV   27,32,30 31

Due to misaligned fields, the graph output is difficult to read.
Additionally, the "operation type-specific" field is always empty, as
its entries were removed in commit 986f8c7ff2 ("teflon: Support multiple
graph inputs and outputs").

Properly align the input and output fields and remove the
"operation type-specific" column. Also, widen the "type" field to
accommodate the longest currently supported operation name. The resulting
output looks like this:

idx type            inputs               outputs
==========================================================================
  0 CONV            88,8,6               7
  1 DWCONV          7,35,34              33
  2 CONV            33,38,36             37
  3 DWCONV          37,41,40             39
  [...]
 20 CONV            9,14,12              13
 21 DWCONV          13,17,16             15
 22 CONV            15,20,18             19
 23 DWCONV          19,23,22             21
 24 CONV            21,26,24             25
 25 DWCONV          25,29,28             27
 26 CONV            27,32,30             31

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38942>
 2026-01-10 14:05:48 +00:00
Konstantin Seurer
077292f65b radv/bvh: Use box16 nodes when bvh8 is not used
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Using box16 nodes trades bvh quality for memory bandwidth which seems to
be roughly equal in performance.

Stats assuming box16 nodes are as expensive as box32 nodes:
Totals from 7668 (79.68% of 9624) affected BVHs:
compacted_size: 951666944 -> 742347648 (-22.00%)
max_depth: 57606 -> 57615 (+0.02%)
sah: 129114796242 -> 129998517775 (+0.68%); split: -0.00%, +0.68%
scene_sah: 188564162 -> 192063633 (+1.86%); split: -0.02%, +1.88%
box16_node_count: 0 -> 3270600 (+inf%)
box32_node_count: 3365707 -> 95100 (-97.17%)

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37883>
 2026-01-10 11:36:28 +01:00
Konstantin Seurer
543a88af99 radv/bvh: Add radv_aabb16 and use it for box16 nodes 
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37883>
 2026-01-10 11:36:19 +01:00
Konstantin Seurer
fefdad9249 radv/rra: Count box16 nodes properly 
Otherwise rra won't allocate memory when loading the capture.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37883>
 2026-01-10 11:34:18 +01:00
Konstantin Seurer
39d58a55a7 aco: Add support to f2f16 with rtpi/rtni 
Those rounding modes are needed when computing 16-bit bounding boxes
since the bounding box must not get smaller.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37883>
 2026-01-10 11:34:12 +01:00
Konstantin Seurer
f156743b0f spirv: Add internal f2f16 opcodes 
The OpFConvert+FPRoundingModeRTP/FPRoundingModeRTN cannot be used
because GL_EXT_spirv_intrinsics does not allow decorations. Instead,
we need opcodes that encode the rounding mode so that they can be used
in glsl code.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37883>
 2026-01-10 11:34:07 +01:00
Konstantin Seurer
6d9cd36db6 nir: Add f2f16_ru/rd opcodes 
Those are variants of f2f16 that always round up/down. Constant folding
requires nextafter that supports half floats (util_nextafter).

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37883>
 2026-01-10 11:33:23 +01:00
Mel Henning
78c8b8f131 nak/instr_sched_prepass: Fix RegOut special case
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This fixes the register count accounting to match the equivalent
special case in liveness.rs

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14614
Fixes: b55b8da012 ("nak: Add a prepass instruction scheduler")
Acked-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39220>
 2026-01-09 23:31:45 +00:00
Mel Henning
9ff8ee49f4 nak: Copy-prop bindless cbuf handles 
Totals:
CodeSize: 4503463376 -> 4502059168 (-0.03%); split: -0.03%, +0.00%
Number of GPRs: 11377380 -> 11377668 (+0.00%); split: -0.00%, +0.00%
Static cycle count: 2871017064 -> 2870884663 (-0.00%); split: -0.01%, +0.00%
Spills to reg: 210798 -> 210728 (-0.03%)
Fills from reg: 200514 -> 200489 (-0.01%)
Max warps/SM: 7361864 -> 7361904 (+0.00%)

Totals from 28087 (14.27% of 196789) affected shaders:
CodeSize: 870417856 -> 869013648 (-0.16%); split: -0.17%, +0.01%
Number of GPRs: 2273399 -> 2273687 (+0.01%); split: -0.00%, +0.02%
Static cycle count: 780733864 -> 780601463 (-0.02%); split: -0.04%, +0.02%
Spills to reg: 135380 -> 135310 (-0.05%)
Fills from reg: 131832 -> 131807 (-0.02%)
Max warps/SM: 891108 -> 891148 (+0.00%)

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39122>
 2026-01-09 23:08:29 +00:00
Mel Henning
e92ab5db56 nak/copy_prop: Split out prop_to_ssa_values helper 
Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39122>
 2026-01-09 23:08:29 +00:00
Aaron Ruby
ab01793281 gfxstream: Partial revert of "gfxstream: revert "gfxstream: Add Vulkan func/structs for passing debugging data to host"" 
i.e. A revert^2 of 8f8bc7ca3b, to undo the
revert in cerealgenerator.py.

It needs to track latest file-naming in upstream host gfxstream:
https://github.com/google/gfxstream/blob/main/host/common/include/gfxstream/host/process_resources.h

Reviewed-by: Gurchetan Singh <gurchetansingh@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39241>
 2026-01-09 22:50:18 +00:00
Karol Herbst
777f971d68 docs: reorder and add zink to CL subgroup entries
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Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38015>
 2026-01-09 21:53:28 +00:00