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teflon: Improve dumped graph formatting
Currently, the graph dumped with ``TEFLON_DEBUG=verbose`` has the
following appearance:
idx type inputs outputs operation type-specific
================================================================================================
0 CONV 88,8,6 7
1 DWCONV 7,35,34 33
2 CONV 33,38,36 37
3 DWCONV 37,41,40 39
[...]
20 CONV 9,14,12 13
21 DWCONV 13,17,16 15
22 CONV 15,20,18 19
23 DWCONV 19,23,22 21
24 CONV 21,26,24 25
25 DWCONV 25,29,28 27
26 CONV 27,32,30 31
Due to misaligned fields, the graph output is difficult to read.
Additionally, the "operation type-specific" field is always empty, as
its entries were removed in commit 986f8c7ff2 ("teflon: Support multiple
graph inputs and outputs").
Properly align the input and output fields and remove the
"operation type-specific" column. Also, widen the "type" field to
accommodate the longest currently supported operation name. The resulting
output looks like this:
idx type inputs outputs
==========================================================================
0 CONV 88,8,6 7
1 DWCONV 7,35,34 33
2 CONV 33,38,36 37
3 DWCONV 37,41,40 39
[...]
20 CONV 9,14,12 13
21 DWCONV 13,17,16 15
22 CONV 15,20,18 19
23 DWCONV 19,23,22 21
24 CONV 21,26,24 25
25 DWCONV 25,29,28 27
26 CONV 27,32,30 31
Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38942>
This commit is contained in:
Maíra Canal
Marge Bot
parent
077292f65b
commit
104d1a0d4b
1 changed files with 30 additions and 25 deletions
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@ -376,74 +376,79 @@ dump_graph(struct pipe_tensor *tensors, unsigned tensor_count, struct pipe_ml_op
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}
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teflon_debug("\n");
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teflon_debug("%3s %-6s %25s %25s %s\n", "idx", "type", "inputs", "outputs", "operation type-specific");
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teflon_debug("================================================================================================\n");
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teflon_debug("%3s %-15s %-20s %-20s\n", "idx", "type", "inputs", "outputs");
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teflon_debug("==========================================================================\n");
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for (int i = 0; i < operation_count; i++) {
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teflon_debug("%3d ", i);
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switch (operations[i].type) {
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case PIPE_ML_OPERATION_TYPE_ADD:
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teflon_debug("%-6s ", "ADD");
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teflon_debug("%-15s ", "ADD");
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break;
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case PIPE_ML_OPERATION_TYPE_CONVOLUTION:
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teflon_debug("%-6s ", operations[i].conv.depthwise ? "DWCONV" : "CONV");
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teflon_debug("%-15s ", operations[i].conv.depthwise ? "DWCONV" : "CONV");
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break;
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case PIPE_ML_OPERATION_TYPE_CONCATENATION:
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teflon_debug("%-6s ", "CONCAT");
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teflon_debug("%-15s ", "CONCAT");
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break;
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case PIPE_ML_OPERATION_TYPE_POOLING:
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teflon_debug("%-6s ", "POOL");
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teflon_debug("%-15s ", "POOL");
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break;
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case PIPE_ML_OPERATION_TYPE_SPLIT:
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teflon_debug("%-6s ", "SPLIT");
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teflon_debug("%-15s ", "SPLIT");
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break;
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case PIPE_ML_OPERATION_TYPE_PAD:
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teflon_debug("%-6s ", "PAD");
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teflon_debug("%-15s ", "PAD");
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break;
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case PIPE_ML_OPERATION_TYPE_FULLY_CONNECTED:
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teflon_debug("%-6s ", "FCON");
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teflon_debug("%-15s ", "FCON");
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break;
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case PIPE_ML_OPERATION_TYPE_RESHAPE:
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teflon_debug("%-6s ", "RESHAPE");
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teflon_debug("%-15s ", "RESHAPE");
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break;
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case PIPE_ML_OPERATION_TYPE_RELU:
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teflon_debug("%-6s ", "RELU");
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teflon_debug("%-15s ", "RELU");
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break;
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case PIPE_ML_OPERATION_TYPE_ABSOLUTE:
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teflon_debug("%-6s ", "ABS");
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teflon_debug("%-15s ", "ABS");
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break;
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case PIPE_ML_OPERATION_TYPE_LOGISTIC:
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teflon_debug("%-6s ", "LOG");
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teflon_debug("%-15s ", "LOG");
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break;
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case PIPE_ML_OPERATION_TYPE_SUBTRACT:
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teflon_debug("%-6s ", "SUB");
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teflon_debug("%-15s ", "SUB");
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break;
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case PIPE_ML_OPERATION_TYPE_TRANSPOSE:
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teflon_debug("%-6s ", "TRANSPOSE");
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teflon_debug("%-15s ", "TRANSPOSE");
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break;
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case PIPE_ML_OPERATION_TYPE_STRIDED_SLICE:
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teflon_debug("%-6s ", "STRIDED_SLICE");
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teflon_debug("%-15s ", "STRIDED_SLICE");
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break;
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case PIPE_ML_OPERATION_TYPE_RESIZE:
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teflon_debug("%-6s ", "RESIZE");
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teflon_debug("%-15s ", "RESIZE");
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break;
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}
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char *input_buf = ralloc_strdup(NULL, "");
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for (unsigned j = 0; j < operations[i].input_count; j++) {
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teflon_debug("%d", operations[i].input_tensors[j]->index);
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ralloc_asprintf_append(&input_buf, "%d", operations[i].input_tensors[j]->index);
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if (j < operations[i].input_count - 1)
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teflon_debug(",");
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ralloc_asprintf_append(&input_buf, ",");
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}
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teflon_debug(" ");
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char *output_buf = ralloc_strdup(NULL, "");
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for (unsigned j = 0; j < operations[i].output_count; j++) {
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teflon_debug("%d", operations[i].output_tensors[j]->index);
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ralloc_asprintf_append(&output_buf, "%d", operations[i].output_tensors[j]->index);
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if (j < operations[i].output_count - 1)
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teflon_debug(",");
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ralloc_asprintf_append(&output_buf, ",");
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}
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teflon_debug("\n");
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teflon_debug("%-20s %-20s\n", input_buf, output_buf);
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ralloc_free(input_buf);
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ralloc_free(output_buf);
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}
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teflon_debug("\n");
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}
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@ -740,7 +745,7 @@ PrepareDelegate(TfLiteContext *tf_context, TfLiteDelegate *tf_delegate)
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for (int i = 0; i < tf_context->tensors_size; i++)
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fill_tensor(delegate, tf_context, &delegate->tensors[i], i);
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teflon_debug("%3s %7s %3s %-11s %s\n", "idx", "type", "ver", "support", "inputs");
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teflon_debug("%3s %-15s %3s %-11s %s\n", "idx", "type", "ver", "support", "inputs");
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teflon_debug("================================================================================================\n");
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// Get a list of supported nodes.
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@ -756,7 +761,7 @@ PrepareDelegate(TfLiteContext *tf_context, TfLiteDelegate *tf_delegate)
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supported = check_op_support(tf_delegate, tf_context, node, registration);
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teflon_debug("%3d %7s v%-2d %-11s in:", node_index,
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teflon_debug("%3d %-15s v%-2d %-11s in:", node_index,
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tflite_builtin_op_name(registration->builtin_code),
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registration->version,
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supported ? "supported" : "unsupported");
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