Commit graph

177262 commits

Author SHA1 Message Date
Karol Herbst
f90f68aa1c rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24982>
2023-09-02 10:11:24 +00:00
Georg Lehmann
3a715cc9d2 nir: add nir_scalar_equal
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
2023-09-02 00:26:31 +00:00
Georg Lehmann
bce9bba90d nir: add nir_scalar intrinsic helpers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
2023-09-02 00:26:31 +00:00
David Heidelberg
1ae3c40732 docs: add LAVA farm informations
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
2023-09-01 23:58:51 +00:00
David Heidelberg
1a990e21c8 Revert "ci: disable a660 jobs"
This reverts commit 209ed8eace.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
2023-09-01 23:58:51 +00:00
Lionel Landwerlin
4066f05fe4 anv: enable standard Y tiles
We kept those tilings disabled up to know. Now that ISL has proper
support for them, remove this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
db4488a2dc anv: Align memory VA to support for Ys, Tile64 tiled images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Aditya Swarup
e03f3b646c isl: enable Tile64 for 3D images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
e956f6ad30 intel/isl: Allow Ys tiling
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
4ac46dbb46 isl: reorder tiling selection
Select tilings in this order :
  - recommended Y tilings
  - Yf tilings
  - Ys/Tile64 tilings
  - legacy tilings (W, X) & Linear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
af559c48d3 intel/aux_map: correctly program tiling mode for Ys
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
3c6d003d9f blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling
The data in Ys/Yf/Tile64 tiled images is arranged differently for 2D &
3D images. Therefore we cannot assume that we will use 2D images for
blits/copies.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
e182f5770d isl: disable CCS on Ys/Yf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
4e36aa507e isl: disable miptails on gfx12 with yuv formats
A number of CTS tests are failing, like :

   dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal

Failures are reproduced on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
aa31683dde isl: disallow miptails on planar formats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
7ee41c162d isl: add Gfx12/12.5 restriction on 3D surfaces & compression
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
63c86a95b2 intel/isl: Disallow CCS on 3D surfaces with miptails
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
46f45d62d1 intel/isl: Start using miptails
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
a42d808b71 intel/isl: Support miptails in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
866af3d8fa isl: make isl_surf_get_uncompressed_surf robust to argument accesses
Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
988fa2006a intel/isl: Add support for computing offsets with miptails
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
1ada5f5490 intel/isl: Add a max_miptail_levels field to isl_tile_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
b1862a0964 intel/isl: Add initial data-structure support for miptails
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code.  We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
68ac5c2165 intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
01b50c9dac intel/isl: Support Yf/Ys tiling in surf_fill_state
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
6f90d6d228 intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
4ef7b074e7 intel/isl: Indent uncompressed surface code
We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
9a4e9848ad intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us.  We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
9421998e95 intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
390d53e13f isl: disallow TileYs/Yf on 3D storage images on Gfx9/11
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
15648dcbba isl: add a usage flag to request 2D/3D compatible views
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
7c5015e181 isl: disable Yf/Ys/Tile64 tilings for 1D images
The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
6cde6b1d1a intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
911832e9cf intel/isl: Implement correct tile size calculations for Ys/Yf
The tile size calculations use a clever bit of math to make them short
and simple.  We add unit tests to assert that they identically match the
tables in the PRM.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
e230ef329b intel/isl: Add ICL variants of Yf and Ys tiling
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
fa625aea3d intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s
The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
298e8dee61 isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented
Since this value is 0, it doesn't change anything, but it's just good
practice like we did for Gfx12.5 right above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
3e9f366b70 genxml/gfx12: rename Tiled Resource Mode
To match documentation.

BSpec 46965

TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
cc985bb2ad genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER
This field doesn't exist according to documentation. Only a MBZ.

BSpec 6511

ICL PRMs, Volume 2a - Command Reference: Instructions (Command
Opcodes) 3DSTATE_HIER_DEPTH_BUFFER

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:16 +00:00
Lionel Landwerlin
34d5db0583 anv: add missing ISL storage usage
ISL makes a bunch of decision on programming (MOCS,
RENDER_SURFACE_STATE values) based on this flag. It's important to set
it if we're going to use an image as storage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:16 +00:00
Matt Turner
28c1053c07 intel: Allow using intel_clc from the system
With -Dintel-clc=system, the build system will search for an `intel_clc`
binary and use it instead of building `intel_clc` itself.

This allows Intel Vulkan ray tracing support to be built when cross
compiling without terrible hacks (that would otherwise be necessary due
to `intel_clc`'s dependence on SPIRV-LLVM-Translator, libclc, clang, and
LLVM).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24983>
2023-09-01 21:36:02 +00:00
Karol Herbst
5263802618 rusticl/memory: do not verify pitch for IMAGE1D_BUFFER
Devices might report an image_pitch_alignment of 0 leading to a division
by 0 trap.

Fixes: 06daa03c5c ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>
2023-09-01 20:06:30 +00:00
Eric Engestrom
a8c7a2fb69 ci/amd: split the polaris10 rules into one for each farm
There is now one polaris10 in each farm, so we need two rules for which
one to use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>
2023-09-01 19:35:33 +00:00
Mark Janes
0f291cb6c0 intel: allow reduced memory usage for INTEL_MEASURE
The default batch size was increased to support large numbers of
INTEL_MEASURE snapshots for complex workloads.  Some titles create
large numbers of small secondary command buffers, and quickly exhaust
memory.  An example of this is Dota2, where INTEL_MEASURE increases
the memory usage by a factor of 20.

Allow the user to specify smaller batch sizes and buffer sizes.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24860>
2023-09-01 18:50:24 +00:00
Georg Lehmann
cda5784eb3 aco: use v_cvt_f32_ubyte for signed casts too
The extract is always positive, so signed vs unsigned conversion doesn't matter.

Foz-DB GFX11:
Totals from 167 (0.13% of 133461) affected shaders:
Instrs: 401631 -> 401225 (-0.10%)
CodeSize: 2107256 -> 2104344 (-0.14%)
VGPRs: 13320 -> 13332 (+0.09%)
Latency: 6468063 -> 6467241 (-0.01%)
InvThroughput: 801854 -> 801653 (-0.03%)
Copies: 13926 -> 13927 (+0.01%); split: -0.08%, +0.09%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24893>
2023-09-01 17:21:57 +00:00
Nanley Chery
144c2d4e4a anv: Initialize the clear color more often for FCV
Instead of only initializing the clear color when the first subresource
is accessed, initialize it for every FCV-enabled subresource. This is
needed because writes to any subresource may be converted to fast
clears.

Now that init_fast_clear_color is called for every subresource, we take
care not to stomp on the fast-clear-tracking state of the first
subresource by moving the code which updates it outside of
init_fast_clear_color.

Now init_fast_clear_color does just what it says: initializes the fast
clear color.

This fixes the regression introduced with commit 57445adc89,
("anv: Re-enable CCS_E on TGL+").

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8461
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24857>
2023-09-01 16:34:22 +00:00
Samuel Pitoiset
223d00fe0a radv/ci: re-enable vkcts-polaris10-valve
This was disabled a long time ago because of unknown GPU hangs during
boot but it seems stable again for some reasons.

This also bumps the job timeouts to make sure it will be able to finish.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24968>
2023-09-01 15:14:58 +00:00
Karol Herbst
46c17a8e54 rusticl/queue: properly implement clCreateCommandQueueWithProperties
It didn't do any of the error checking, but it was supposed to be. Also
the error checking was slightly wrong and we should return
CL_INVALID_QUEUE_PROPERTIES instead of CL_INVALID_VALUE for unsupported
properties.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24991>
2023-09-01 13:51:22 +00:00
Samuel Pitoiset
969f7b97fd zink/ci: add zink-radv-polaris10-valve
This introduces Zink/RADV testing on Polaris10!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24976>
2023-09-01 12:52:42 +00:00
Feng Jiang
a1a2aac3a3 meson: Move video to separate section in meson configuration summary
Since the video configuration is shared by multiple video APIs, not
just vulkan, move it to a separate section.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24598>
2023-09-01 11:57:37 +00:00