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intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
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2 changed files with 26 additions and 1 deletions
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@ -48,9 +48,21 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
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ISL_TILING_4_BIT |
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ISL_TILING_64_BIT;
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if (isl_surf_usage_is_depth_or_stencil(info->usage))
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if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
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*flags &= ISL_TILING_4_BIT | ISL_TILING_64_BIT;
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/* We choose to avoid Tile64 for 3D depth/stencil buffers. The swizzle
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* for Tile64 is dependent on the image dimension. So, reads and writes
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* should specify the same dimension to consistently interpret the data.
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* This is not possible for 3D depth/stencil buffers however. Such
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* buffers can be sampled from with a 3D view, but rendering is only
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* possible with a 2D view due to the limitations of
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* 3DSTATE_(DEPTH|STENCIL)_BUFFER.
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*/
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if (info->dim == ISL_SURF_DIM_3D)
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*flags &= ~ISL_TILING_64_BIT;
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}
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if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
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*flags &= ~ISL_TILING_64_BIT;
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@ -238,6 +238,19 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
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*flags &= ISL_TILING_ANY_Y_MASK;
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}
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if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
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/* We choose to avoid Yf/Ys for 3D depth/stencil buffers. The swizzles
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* for the Yf and Ys tilings are dependent on the image dimension. So,
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* reads and writes should specify the same dimension to consistently
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* interpret the data. This is not possible for 3D depth/stencil buffers
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* however. Such buffers can be sampled from with a 3D view, but
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* rendering is only possible with a 2D view due to the limitations of
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* 3DSTATE_(DEPTH|STENCIL)_BUFFER.
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*/
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if (info->dim == ISL_SURF_DIM_3D)
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*flags &= ~ISL_TILING_STD_Y_MASK;
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}
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if (isl_surf_usage_is_stencil(info->usage)) {
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if (ISL_GFX_VER(dev) >= 12) {
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/* Stencil requires Y. */
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