fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 13:10:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/isl: Add ICL variants of Yf and Ys tiling

Browse source 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
This commit is contained in:
Jason Ekstrand 2018-03-06 21:04:50 -08:00 • committed by Marge Bot
parent fa625aea3d
commit e230ef329b
6 changed files with 48 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
src/intel/isl/isl.c
View file

@ -502,8 +502,11 @@ isl_tiling_get_info(enum isl_tiling tiling,
break;
case ISL_TILING_SKL_Yf:
case ISL_TILING_SKL_Ys: {
bool is_Ys = tiling == ISL_TILING_SKL_Ys;
case ISL_TILING_SKL_Ys:
case ISL_TILING_ICL_Yf:
case ISL_TILING_ICL_Ys: {
bool is_Ys = tiling == ISL_TILING_SKL_Ys ||
tiling == ISL_TILING_ICL_Ys;
assert(bs > 0);
unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
@ -748,7 +751,9 @@ isl_surf_choose_tiling(const struct isl_device *dev,
CHOOSE(ISL_TILING_4);
CHOOSE(ISL_TILING_64);
CHOOSE(ISL_TILING_ICL_Ys);
CHOOSE(ISL_TILING_SKL_Ys);
CHOOSE(ISL_TILING_ICL_Yf);
CHOOSE(ISL_TILING_SKL_Yf);
CHOOSE(ISL_TILING_Y0);
CHOOSE(ISL_TILING_X);
@ -1138,7 +1143,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
assert(dim_layout == ISL_DIM_LAYOUT_GFX4_2D ||
dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
if (tiling == ISL_TILING_SKL_Ys && info->samples > 1)
if ((tiling == ISL_TILING_SKL_Ys ||
tiling == ISL_TILING_ICL_Ys) && info->samples > 1)
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
switch (msaa_layout) {
@ -1837,7 +1843,7 @@ _isl_notify_failure(const struct isl_surf_init_info *surf_info,
snprintf(msg + ret, sizeof(msg) - ret,
" extent=%ux%ux%u dim=%s msaa=%ux levels=%u rpitch=%u fmt=%s "
"usages=%s%s%s%s%s%s%s%s%s%s%s%s%s%s "
"tiling_flags=%s%s%s%s%s%s%s%s%s%s%s",
"tiling_flags=%s%s%s%s%s%s%s%s%s%s%s%s%s",
surf_info->width, surf_info->height,
surf_info->dim == ISL_SURF_DIM_3D ?
surf_info->depth : surf_info->array_len,
@ -1868,6 +1874,8 @@ _isl_notify_failure(const struct isl_surf_init_info *surf_info,
PRINT_TILING(Y0, "Y0"),
PRINT_TILING(SKL_Yf, "skl-Yf"),
PRINT_TILING(SKL_Ys, "skl-Ys"),
PRINT_TILING(ICL_Yf, "icl-Yf"),
PRINT_TILING(ICL_Ys, "icl-Ys"),
PRINT_TILING(4, "4"),
PRINT_TILING(64, "64"),
PRINT_TILING(HIZ, "hiz"),
@ -3743,6 +3751,8 @@ isl_tiling_to_name(enum isl_tiling tiling)
[ISL_TILING_Y0] = "Y0",
[ISL_TILING_SKL_Yf] = "SKL-Yf",
[ISL_TILING_SKL_Ys] = "SKL-Ys",
[ISL_TILING_ICL_Yf] = "ICL-Yf",
[ISL_TILING_ICL_Ys] = "ICL-Ys",
[ISL_TILING_4] = "4",
[ISL_TILING_64] = "64",
[ISL_TILING_HIZ] = "hiz",

12
src/intel/isl/isl.h
View file

@ -578,6 +578,8 @@ enum isl_tiling {
ISL_TILING_Y0, /**< Legacy Y tiling */
ISL_TILING_SKL_Yf, /**< Standard 4K tiling. The 'f' means "four". */
ISL_TILING_SKL_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
ISL_TILING_ICL_Yf, /**< Standard 4K tiling. The 'f' means "four". */
ISL_TILING_ICL_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
ISL_TILING_4, /**< 4K tiling. */
ISL_TILING_64, /**< 64K tiling.*/
ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
@ -596,6 +598,8 @@ typedef uint32_t isl_tiling_flags_t;
#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
#define ISL_TILING_SKL_Yf_BIT (1u << ISL_TILING_SKL_Yf)
#define ISL_TILING_SKL_Ys_BIT (1u << ISL_TILING_SKL_Ys)
#define ISL_TILING_ICL_Yf_BIT (1u << ISL_TILING_ICL_Yf)
#define ISL_TILING_ICL_Ys_BIT (1u << ISL_TILING_ICL_Ys)
#define ISL_TILING_4_BIT (1u << ISL_TILING_4)
#define ISL_TILING_64_BIT (1u << ISL_TILING_64)
#define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
@ -607,11 +611,15 @@ typedef uint32_t isl_tiling_flags_t;
/** Any Y tiling, including legacy Y tiling. */
#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
ISL_TILING_SKL_Yf_BIT | \
ISL_TILING_SKL_Ys_BIT)
ISL_TILING_SKL_Ys_BIT | \
ISL_TILING_ICL_Yf_BIT | \
ISL_TILING_ICL_Ys_BIT)
/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
#define ISL_TILING_STD_Y_MASK (ISL_TILING_SKL_Yf_BIT | \
ISL_TILING_SKL_Ys_BIT)
ISL_TILING_SKL_Ys_BIT | \
ISL_TILING_ICL_Yf_BIT | \
ISL_TILING_ICL_Ys_BIT)
/** @} */
/**

2
src/intel/isl/isl_drm.c
View file

@ -49,6 +49,8 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
case ISL_TILING_W:
case ISL_TILING_SKL_Yf:
case ISL_TILING_SKL_Ys:
case ISL_TILING_ICL_Yf:
case ISL_TILING_ICL_Ys:
case ISL_TILING_4:
case ISL_TILING_64:
case ISL_TILING_GFX12_CCS:

20
src/intel/isl/isl_gfx7.c
View file

@ -201,12 +201,23 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
if (ISL_GFX_VER(dev) >= 12) {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
ISL_TILING_ANY_Y_MASK;
ISL_TILING_Y0_BIT |
ISL_TILING_ICL_Yf_BIT |
ISL_TILING_ICL_Ys_BIT;
} else if (ISL_GFX_VER(dev) >= 11) {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
ISL_TILING_W_BIT |
ISL_TILING_Y0_BIT |
ISL_TILING_ICL_Yf_BIT |
ISL_TILING_ICL_Ys_BIT;
} else if (ISL_GFX_VER(dev) >= 9) {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
ISL_TILING_W_BIT |
ISL_TILING_ANY_Y_MASK;
ISL_TILING_Y0_BIT |
ISL_TILING_SKL_Yf_BIT |
ISL_TILING_SKL_Ys_BIT;
} else {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
@ -219,6 +230,8 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
*/
*flags &= ~ISL_TILING_SKL_Yf_BIT; /* FINISHME[SKL]: Support Yf */
*flags &= ~ISL_TILING_SKL_Ys_BIT; /* FINISHME[SKL]: Support Ys */
*flags &= ~ISL_TILING_ICL_Yf_BIT; /* FINISHME[ICL]: Support Yf */
*flags &= ~ISL_TILING_ICL_Ys_BIT; /* FINISHME[ICL]: Support Ys */
if (isl_surf_usage_is_depth(info->usage)) {
/* Depth requires Y. */
@ -250,7 +263,8 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
* completeness.
*/
*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
ISL_TILING_Y0_BIT | ISL_TILING_SKL_Yf_BIT);
ISL_TILING_Y0_BIT |
ISL_TILING_SKL_Yf_BIT | ISL_TILING_ICL_Yf_BIT);
} else {
/* Before Skylake, the display engine does not accept Y */
*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);

3
src/intel/isl/isl_gfx9.c
View file

@ -41,7 +41,8 @@ gfx9_calc_std_image_alignment_sa(const struct isl_device *dev,
assert(isl_tiling_is_std_y(tiling));
const uint32_t bpb = fmtl->bpb;
const uint32_t is_Ys = tiling == ISL_TILING_SKL_Ys;
const uint32_t is_Ys = tiling == ISL_TILING_SKL_Ys ||
tiling == ISL_TILING_ICL_Ys;
switch (info->dim) {
case ISL_SURF_DIM_1D:

4
src/intel/isl/isl_surface_state.c
View file

@ -49,9 +49,11 @@ static const uint8_t isl_encode_tiling[] = {
[ISL_TILING_64] = TILE64,
#else
[ISL_TILING_Y0] = YMAJOR,
[ISL_TILING_ICL_Yf] = YMAJOR,
[ISL_TILING_ICL_Ys] = YMAJOR,
[ISL_TILING_SKL_Yf] = YMAJOR,
[ISL_TILING_SKL_Ys] = YMAJOR,
#endif
#endif /* GFX_VERx10 < 125 */
#if GFX_VER <= 11
[ISL_TILING_W] = WMAJOR,
#endif