Commit graph

1677 commits

Author SHA1 Message Date
Georg Lehmann
63d199a01e nir: remove special fp_math_ctrl rules
All opcodes should now respect the nan/inf/sz preserving flags.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39641>
2026-02-10 18:42:02 +00:00
Daniel Schürmann
4ca7ee7bd7 nir/opt_load_store_vectorize: Allow to vectorize at most one entry of each type across blocks
The idea is to initialize the vectorization table with one
entry from the previous blocks if it's the same for all predecessors.
In order to not speculatively load out-of-bounds, backends need to
set a new bounds_checked_modes option indicating variable modes
for which per-component bounds checks are supported.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39373>
2026-02-06 10:16:50 +00:00
Timothy Arceri
0410377b63 nir: make nir_add_inlinable_uniforms() private
Hasn't been used externally since e93592dc62

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39664>
2026-02-05 23:19:28 +00:00
Timothy Arceri
257875034d nir: make nir_collect_src_uniforms() private
Hasn't been used externally since e93592dc62

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39664>
2026-02-05 23:19:28 +00:00
Karol Herbst
4add3959e9 nir: add BASE to nvidia memory intrinsics
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39525>
2026-02-03 22:23:50 +00:00
Karol Herbst
e779538ad2 nir: add nvidia IO intrinsics
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39525>
2026-02-03 22:23:50 +00:00
Georg Lehmann
575affaf48 nir/search: gather union of all fp_math_ctrl
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
2026-01-31 15:30:25 +00:00
Kenneth Graunke
b844082017 nir: Add a round_up_components callback to load/store vectorization
By default, load/store vectorization uses nir_round_up_components()
to round up loads and possibly writemasked stores to the next valid
NIR vector width.  However, some backends may not support load/stores
at all sizes.  For example, older Intel supports only power-of-two
vector widths.  Newer Intel also supports vec2 and vec3, but not
vec5/6/7.  By providing a callback, backends can request promotion
to their next supported memory load/store vector width.

The existing "should we vectorize?" callback should continue to return
false for unsupported vector widths (i.e. beyond the maximum supported).
With this new callback, they do not need to say "no" to vectorization
that would normally produce an unsupported count (e.g. vec5/6/7) but
instead request that the component count be rounded up appropriately.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
2026-01-27 16:08:36 +00:00
Kenneth Graunke
e23a83b786 nir: Add load/store vectorizer option for rounding up masked stores
This adds a new option, round_up_store_components, which rounds up the
number of components for stores that support writemasking to the next
valid vector size.  For example, vec4+vec2 stores would round up from
6 components (which wouldn't be supported) to a full supportable vec8
store, relying on writemasking to ensure the correct pieces are written.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
2026-01-27 16:08:36 +00:00
Emma Anholt
e922c2cabc nir,spirv: Add support for SPV_QCOM_image_processing.
Initial work was done by Mark Collins, which I significantly rewrote.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
2026-01-27 02:00:40 +00:00
Connor Abbott
3208cc80b1 nir: Move is is_compact() out of unlower_io_to_vars
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39328>
2026-01-21 20:54:13 +00:00
Daniel Schürmann
598928d7e7 nir/loop_analyze: determine whether all control flow gets eliminated upon loop unrolling
Totals from 17 (0.02% of 79839) affected shaders: (Navi48)

MaxWaves: 241 -> 243 (+0.83%); split: +5.81%, -4.98%
Instrs: 44198 -> 43786 (-0.93%); split: -8.19%, +7.26%
CodeSize: 230284 -> 226900 (-1.47%); split: -10.55%, +9.08%
VGPRs: 2152 -> 2524 (+17.29%); split: -3.90%, +21.19%
Scratch: 718848 -> 0 (-inf%)
Latency: 128977 -> 145720 (+12.98%); split: -2.12%, +15.10%
InvThroughput: 206804 -> 254250 (+22.94%); split: -0.32%, +23.27%
VClause: 1296 -> 1309 (+1.00%); split: -28.09%, +29.09%
SClause: 835 -> 833 (-0.24%)
Copies: 6284 -> 3630 (-42.23%); split: -44.51%, +2.28%
Branches: 1003 -> 961 (-4.19%)
PreSGPRs: 1003 -> 996 (-0.70%); split: -1.20%, +0.50%
PreVGPRs: 1510 -> 2130 (+41.06%)
VALU: 23577 -> 24309 (+3.10%); split: -6.26%, +9.37%
SALU: 5875 -> 5688 (-3.18%); split: -6.26%, +3.08%
VMEM: 3679 -> 3001 (-18.43%); split: -33.27%, +14.84%
SMEM: 1632 -> 1631 (-0.06%)
VOPD: 23 -> 24 (+4.35%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38659>
2026-01-21 14:20:06 +00:00
Alyssa Rosenzweig
4e59199cbb nir: add nir_is_shared_access helper
This is helpful to identify shared mem access for writing more generic code
operating on nir intrinsics.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39219>
2026-01-09 20:51:12 +00:00
Georg Lehmann
a706769a0b nir: move exact bit to nir_fp_math_control
Unifies nir per instruction float control.

In the future this can be split into contract/reassoc/transform
like SPIR-V.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (except SPIR-V)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:57 +00:00
Georg Lehmann
eb4737a1dd nir: add nir_alu_instr_is_exact helper
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:57 +00:00
Georg Lehmann
b70294b91f nir: document signed zero, inf, nan preserve flags
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:56 +00:00
Timur Kristóf
2ecb7a9e18 nir: Add pass to lower workgroup size
Lowers a shader to use a smaller workgroup to do the same work,
while it will still appear as a bigger workgroup to applications.

To achieve this, the pass augments the CF of the shader
so that each real subgroup will execute two or more logical
subgroups. A logical subgroup represents what the application
can observe as a subgroup.

The size of a logical subgroup is the same as a real subgroup.
Only one logical subgroup may be executed per real subgroup
at the same time. This ensures that all subgroup operations
keep working and the subgroup invocation ID stays the same.

- When the CF contains barriers, we can't just repeat
  the code and we need to augment each CF node individually
  so that they are aware of logical subgroups.

- In case parts of the CF don't contain any barriers, we can simply
  repeat and predicate that CF for each logical subgroup.
  It is technically not necessary to implement this strategy, but
  in practice it helps reduce the amount of branches in the shader
  and therefore improves compile times.

The pass is mainly intended for working around HW limitations,
for example when the HW has an upper limit on the workgroup size
or doesn't support workgroups at all, but the API requires a
certain minimum.

Notes:
- Only applicable to shader stages that use workgroups
- Hits an assertion when called on smaller workgroups
- Always flattens workgroup size to 1D
- Creates local variables
- Does not change subgroup size
- Variable workgroup size not supported yet, maybe later

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37985>
2026-01-02 13:33:54 -06:00
Timur Kristóf
2b62738b9b nir: Add new nir_remove_outputs pass
Introduce a new NIR pass called nir_remove_outputs which works on
lowered I/O intrinsics and can remove any output varying or sysval.
This is meant to replace custom solutions in drivers,
such as radv_remove_varyings and similar.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33928>
2026-01-01 21:25:42 -06:00
Georg Lehmann
5e8cc19a3b nir: remove per shader float fast math flags
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
These were redundant with the per alu fast math flags.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39026>
2025-12-29 10:57:06 +00:00
Georg Lehmann
f3290219ab nir: use a seperate enum for per alu floating point math control
We don't need one bit per bitsize per instruction if only one actually
matters in the end.

First step towards moving NIR in the direction of full float_controls2
only.

Also rename this from fp_fast_math, because that name implied that 0 is
the no fast math mode, while the opposite was the case.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39026>
2025-12-29 10:57:05 +00:00
Georg Lehmann
4d8cc7d82e nir/divergence: add nir_def_is_divergent_at_use_block helper
For cases where the block we are interested in is not the immediate block
of the nir_src.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38974>
2025-12-19 20:23:23 +00:00
Emma Anholt
5a09abe890 nir: Introduce nir_lower_vars_to_scratch_global().
This lets the driver make a more informed decision about which vars to
lower to scratch based on the vars available to spill.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37245>
2025-12-17 19:50:28 +00:00
Emma Anholt
059d301c79 nir: Drop the mode argument of nir_lower_vars_to_scratch().
It only makes sense for function temps, and that's the only way it's been
used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37245>
2025-12-17 19:50:28 +00:00
Marek Olšák
9ac8e643d6 nir/lower_io: explain properly how nir_lower_io_lower_64bit_to_32* options work
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38916>
2025-12-13 06:41:59 +00:00
Marek Olšák
41d127b9e8 nir/lower_io: remove unused option nir_lower_io_lower_64bit_float_to_32
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38916>
2025-12-13 06:41:59 +00:00
Iván Briano
a7280ab590 nir: add nir_lower_single_sampled::lower_sample_mask_in option
GLSL defines gl_SampleMaskIn as :
   "a fragment language that indicates the set of samples covered
    by the primitive generating the fragment during multisample
    rasterization"

when variable rate shading is enabled, a single invocation might cover
multiple samples. The lowering done in nir_lower_single_sampled() does
not account for that case, so add an option to selectively disable it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38641>
2025-12-11 22:50:10 +00:00
Mel Henning
263a82f49b nir: Add nir_deref_instr_is_arr() helper
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38856>
2025-12-10 22:07:44 +00:00
Marek Olšák
9a2f1be814 nir: add FRAG_RESULT_DUAL_SRC_BLEND and an option to use it
This is potentially nicer for some drivers. AMD drivers will use it.

mesa_frag_result_get_color_index will be used often.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38604>
2025-12-10 19:16:46 +00:00
Marek Olšák
0c400fbed9 nir: give nir_lower_clip_cull_distance_array_vars a better name
also rename the file

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38465>
2025-12-10 05:16:34 +00:00
Marek Olšák
74995eb64d nir: split gathering array sizes from nir_lower_clip_cull_distance_array_vars
nir_lower_clip_cull_distance_array_vars was sneakily updating
shader_info::clip/cull_distance_array_size.

This moves the gathering into a new function
nir_gather_clip_cull_distance_sizes_from_vars.

v2: remove assertions that prevented nir_lower_clip_cull_distance_array_vars
    from being used with non-compact arrays

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38465>
2025-12-10 05:16:34 +00:00
Connor Abbott
bd821b9a17 nir, tu: Add and use load_frag_coord_gmem_ir3
We used load_frag_coord_unscaled_ir3 for loading the fragment coord for
input attachments in GMEM, where the normal scaling for gl_FragCoord
shouldn't be used. However with custom resolve a different scaling will
apply to attachments in GMEM. Separate "unscaled" from "gmem" and rename
the NIR options, in preparation for this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
2025-12-08 20:44:45 +00:00
Arcady Goldmints-Orlov
0df8aa940c nir: Use nir_shader_intrinsics_pass in nir_lower_io_to_scalar
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38816>
2025-12-05 22:30:22 +00:00
Faith Ekstrand
4711e5954e nir: Always use sysvals in lower_input_attachments()
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
The last holdouts of the var options are gone so we can just emit the
system values.  This is overall simpler as it confines all the sysval to
var logic to nir_lower_sysvals_to_varyings().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38562>
2025-11-29 00:50:34 +00:00
Faith Ekstrand
701a9c269e nir: Add LAYER_ID and VIEW_INDEX to nir_lower_sysvals_to_varyings()
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38562>
2025-11-29 00:50:31 +00:00
Marek Olšák
fa0bea5ff8 nir: remove nir_io_add_const_offset_to_base
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
nir_opt_constant_folding does it now.

Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38277>
2025-11-29 00:16:38 +00:00
Alyssa Rosenzweig
2c2dd835af nir/lower_wrmasks: drop callback
All drivers use the same callback and it is unlikely that new drivers will use
this pass since it has better replacements today (lower_mem_bit_sizes for
memory, and it never worked for I/O). This should discourage as much.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38533>
2025-11-26 03:20:39 +00:00
Marek Olšák
5ee9a76058 nir: fix a typo in NIR_PASS_ASSERT_NO_PROGRESS for non-debug builds
Fixes: 4e834b4321 - nir: add NIR_PASS_ASSERT_NO_PROGRESS

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38608>
2025-11-25 21:38:50 +00:00
Dave Airlie
a57753dca2 nir: add coopmat per element operations.
Cooperative matrix as per-element calls that are var args from a spir-v.

These uses the new call op enum.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36992>
2025-11-22 13:16:11 +10:00
Marek Olšák
9e339f4b32 nir: rename nir_lower_indirect_derefs -> nir_lower_indirect_derefs_to_if_else_trees
This describes better what it does.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38471>
2025-11-20 05:42:11 +00:00
Boris Brezillon
98bd0850da nir: Add a pass to downgrade inout PLS vars to {in,out} only ones
Shaders might declare PLS vars as inout but might just use them as in
or out but not both. This pass detects those cases and adjusts the
variable/deref modes accordingly.

This pass should be called before nir_lower_io_vars_to_temporaries(),
otherwise the copy_derefs will be inserted, turning unused variables
into used ones.

This should ideally be called after DCE to make sure we don't leave
PLS inout variables behind.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37110>
2025-11-18 20:25:43 +00:00
Boris Brezillon
ea4d4d2a77 nir: Prepare nir_lower_io_vars_to_temporaries() for optional PLS lowering
Rather than adding another boolean to optionally lower PLS vars, pass
the types we want to lowers through a nir_variable_mode bitmask.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37110>
2025-11-18 20:25:42 +00:00
Ryan Mckeever
75263ce911 nir: add support for pixel_local_storage variables
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37110>
2025-11-18 20:25:42 +00:00
Dave Airlie
438245404c nir: add support for cooperative matrix reduction operations.
This adds some new call operations to handle various parts of the
reductions.

cmat_reduce: is the initial toplevel operation from SPIR-V
this is used after lowering for row/col operation on single hw
supported matrix sizes. The spir-v operation is lowered into
multiple of these on flex dimensions, but also can be lowered into
others.

cmat_reduce_finish:
after multiple reduction operations on a flexible dimension matrix,
there is often subsequent operations on the output matrices to
finish the operation.

cmat_reduce_2x2:
this takes 4 input matrices, and 1 dst to do a 2x2 reduction op.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38389>
2025-11-17 23:33:59 +00:00
Dave Airlie
9385d94bc9 nir: add a flag for functions that are used in cmat calls.
With coopmat2 a bunch of functions need a lot of lowering passes
to happen before they can be lowered, so mark them as to be lowered
later.

Drivers needing these should call the nir_remove_non_cmat_call_entrypoints
where they remove entrypoints now, and call the original nir_remove_non_entrypoints
after lowering coopmat2.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38389>
2025-11-17 23:33:58 +00:00
Dave Airlie
26eaba935d nir: add a cmat call instruction type.
This adds a new instruction type to handle cooperative matrix calls.

This clones the call instr, drops callee, and adds a single metadata
slot and a call operation (dummy only for now).

(Not NACKed by Alyssa)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38389>
2025-11-17 23:33:58 +00:00
Marek Olšák
da52bc466f nir: add nir_separate_merged_clip_cull_io
Only needed by zink. This clip/cull distance separation pass is needed
to remove nir_io_separate_clip_cull_distance_arrays, so that all shared
GLSL code only uses merged clip+cull distance outputs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38452>
2025-11-15 03:30:10 +00:00
Marek Olšák
e372365cf4 nir: rename nir_copy_prop -> nir_opt_copy_prop
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38411>
2025-11-15 02:16:38 +00:00
Marek Olšák
4e834b4321 nir: add NIR_PASS_ASSERT_NO_PROGRESS
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This aborts if a pass would make any progress. It can be used to assert that:
- our minimalist pass invocation loops in drivers are sufficient and don't
  leave any unoptimized code in the shader
- our lowering is sufficient and other passes don't add instructions that
  would cause lowering having to be repeated

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38406>
2025-11-14 21:39:12 +00:00
Connor Abbott
d30ff374a1 nir, glsl: Add support for softfloat32
Based on existing softfloat64 support and Berkeley SoftFloat. This is
targeted at drivers that can't preserve denorms, so operations where
denorm support is irrelevant like conversions to/from integers aren't
handled.

Because the existing mechanism used by Gallium for softfloat64 doesn't
support includes, we unfortunately can't extract common code into a
header. This can be done later if we switch Gallium to using glslang and
spirv-to-nir.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37608>
2025-11-14 19:31:17 +00:00
Konstantin Seurer
b241b26d11 nir: Remove nir_def::parent_instr
This reduces the footprint of nir_def by 8B on 64-bit systems.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38313>
2025-11-12 21:22:13 +00:00