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lavapipe: Remove uniform inlining

Browse source 
This broke with the descriptor rework and it will never work because
uniform buffers are bindless now.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32963>
This commit is contained in:
Konstantin Seurer 2025-01-25 17:11:21 +01:00 • committed by Marge Bot
parent 00e98d74b1
commit e93592dc62
5 changed files with 23 additions and 452 deletions
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156
src/gallium/frontends/lavapipe/lvp_execute.c
View file

@ -82,7 +82,7 @@ struct lvp_render_attachment {
struct rendering_state {
struct pipe_context *pctx;
struct lvp_device *device; //for uniform inlining only
struct lvp_device *device;
struct u_upload_mgr *uploader;
struct cso_context *cso;
@ -98,7 +98,6 @@ struct rendering_state {
bool constbuf_dirty[LVP_SHADER_STAGES];
bool pcbuf_dirty[LVP_SHADER_STAGES];
bool has_pcbuf[LVP_SHADER_STAGES];
bool inlines_dirty[LVP_SHADER_STAGES];
bool vp_dirty;
bool scissor_dirty;
bool ib_dirty;
@ -301,93 +300,8 @@ update_pcbuf(struct rendering_state *state, enum pipe_shader_type pstage,
state->pcbuf_dirty[api_stage] = false;
}
static void
update_inline_shader_state(struct rendering_state *state, enum pipe_shader_type sh, bool pcbuf_dirty)
{
unsigned stage = tgsi_processor_to_shader_stage(sh);
state->inlines_dirty[sh] = false;
struct lvp_shader *shader = state->shaders[stage];
if (!shader || !shader->inlines.can_inline)
return;
struct lvp_inline_variant v;
v.mask = shader->inlines.can_inline;
/* these buffers have already been flushed in llvmpipe, so they're safe to read */
nir_shader *base_nir = shader->pipeline_nir->nir;
if (stage == MESA_SHADER_TESS_EVAL && state->tess_ccw)
base_nir = shader->tess_ccw->nir;
nir_function_impl *impl = nir_shader_get_entrypoint(base_nir);
unsigned ssa_alloc = impl->ssa_alloc;
unsigned count = shader->inlines.count[0];
if (count && pcbuf_dirty) {
unsigned push_size = get_pcbuf_size(state, sh);
for (unsigned i = 0; i < count; i++) {
unsigned offset = shader->inlines.uniform_offsets[0][i];
if (offset < push_size) {
memcpy(&v.vals[0][i], &state->push_constants[offset], sizeof(uint32_t));
}
}
for (unsigned i = count; i < MAX_INLINABLE_UNIFORMS; i++)
v.vals[0][i] = 0;
}
bool found = false;
struct set_entry *entry = _mesa_set_search_or_add_pre_hashed(&shader->inlines.variants, v.mask, &v, &found);
void *shader_state;
if (found) {
const struct lvp_inline_variant *variant = entry->key;
shader_state = variant->cso;
} else {
nir_shader *nir = nir_shader_clone(NULL, base_nir);
NIR_PASS_V(nir, lvp_inline_uniforms, shader, v.vals[0], 0);
lvp_shader_optimize(nir);
impl = nir_shader_get_entrypoint(nir);
if (ssa_alloc - impl->ssa_alloc < ssa_alloc / 2 &&
!shader->inlines.must_inline) {
/* not enough change; don't inline further */
shader->inlines.can_inline = 0;
ralloc_free(nir);
shader->shader_cso = lvp_shader_compile(state->device, shader, nir_shader_clone(NULL, shader->pipeline_nir->nir), true);
_mesa_set_remove(&shader->inlines.variants, entry);
shader_state = shader->shader_cso;
} else {
shader_state = lvp_shader_compile(state->device, shader, nir, true);
struct lvp_inline_variant *variant = mem_dup(&v, sizeof(v));
variant->cso = shader_state;
entry->key = variant;
}
}
switch (sh) {
case MESA_SHADER_VERTEX:
state->pctx->bind_vs_state(state->pctx, shader_state);
break;
case MESA_SHADER_TESS_CTRL:
state->pctx->bind_tcs_state(state->pctx, shader_state);
break;
case MESA_SHADER_TESS_EVAL:
state->pctx->bind_tes_state(state->pctx, shader_state);
break;
case MESA_SHADER_GEOMETRY:
state->pctx->bind_gs_state(state->pctx, shader_state);
break;
case MESA_SHADER_TASK:
state->pctx->bind_ts_state(state->pctx, shader_state);
break;
case MESA_SHADER_MESH:
state->pctx->bind_ms_state(state->pctx, shader_state);
break;
case MESA_SHADER_FRAGMENT:
state->pctx->bind_fs_state(state->pctx, shader_state);
state->noop_fs_bound = false;
break;
case MESA_SHADER_COMPUTE:
state->pctx->bind_compute_state(state->pctx, shader_state);
break;
default: break;
}
}
static void emit_compute_state(struct rendering_state *state)
{
bool pcbuf_dirty = state->pcbuf_dirty[MESA_SHADER_COMPUTE];
if (state->pcbuf_dirty[MESA_SHADER_COMPUTE])
update_pcbuf(state, MESA_SHADER_COMPUTE, MESA_SHADER_COMPUTE);
@ -398,12 +312,8 @@ static void emit_compute_state(struct rendering_state *state)
state->constbuf_dirty[MESA_SHADER_COMPUTE] = false;
}
if (state->inlines_dirty[MESA_SHADER_COMPUTE] &&
state->shaders[MESA_SHADER_COMPUTE]->inlines.can_inline) {
update_inline_shader_state(state, MESA_SHADER_COMPUTE, pcbuf_dirty);
} else if (state->compute_shader_dirty) {
if (state->compute_shader_dirty)
state->pctx->bind_compute_state(state->pctx, state->shaders[MESA_SHADER_COMPUTE]->shader_cso);
}
state->compute_shader_dirty = false;
@ -569,8 +479,6 @@ static void emit_state(struct rendering_state *state)
state->vb_dirty = false;
}
bool pcbuf_dirty[LVP_SHADER_STAGES] = {false};
lvp_forall_gfx_stage(sh) {
if (state->constbuf_dirty[sh]) {
for (unsigned idx = 0; idx < state->num_const_bufs[sh]; idx++)
@ -581,16 +489,10 @@ static void emit_state(struct rendering_state *state)
}
lvp_forall_gfx_stage(sh) {
pcbuf_dirty[sh] = state->pcbuf_dirty[sh];
if (state->pcbuf_dirty[sh])
update_pcbuf(state, sh, sh);
}
lvp_forall_gfx_stage(sh) {
if (state->inlines_dirty[sh])
update_inline_shader_state(state, sh, pcbuf_dirty[sh]);
}
if (state->vp_dirty) {
state->pctx->set_viewport_states(state->pctx, 0, state->num_viewports, state->viewports);
state->vp_dirty = false;
@ -615,9 +517,7 @@ handle_compute_shader(struct rendering_state *state, struct lvp_shader *shader)
state->dispatch_info.block[0] = shader->pipeline_nir->nir->info.workgroup_size[0];
state->dispatch_info.block[1] = shader->pipeline_nir->nir->info.workgroup_size[1];
state->dispatch_info.block[2] = shader->pipeline_nir->nir->info.workgroup_size[2];
state->inlines_dirty[MESA_SHADER_COMPUTE] = shader->inlines.can_inline;
if (!shader->inlines.can_inline)
state->compute_shader_dirty = true;
state->compute_shader_dirty = true;
}
static void handle_compute_pipeline(struct vk_cmd_queue_entry *cmd,
@ -700,53 +600,37 @@ handle_graphics_stages(struct rendering_state *state, VkShaderStageFlagBits shad
switch (vk_stage) {
case VK_SHADER_STAGE_FRAGMENT_BIT:
state->inlines_dirty[MESA_SHADER_FRAGMENT] = state->shaders[MESA_SHADER_FRAGMENT]->inlines.can_inline;
if (!state->shaders[MESA_SHADER_FRAGMENT]->inlines.can_inline) {
state->pctx->bind_fs_state(state->pctx, state->shaders[MESA_SHADER_FRAGMENT]->shader_cso);
state->noop_fs_bound = false;
}
state->pctx->bind_fs_state(state->pctx, state->shaders[MESA_SHADER_FRAGMENT]->shader_cso);
state->noop_fs_bound = false;
break;
case VK_SHADER_STAGE_VERTEX_BIT:
state->inlines_dirty[MESA_SHADER_VERTEX] = state->shaders[MESA_SHADER_VERTEX]->inlines.can_inline;
if (!state->shaders[MESA_SHADER_VERTEX]->inlines.can_inline)
state->pctx->bind_vs_state(state->pctx, state->shaders[MESA_SHADER_VERTEX]->shader_cso);
state->pctx->bind_vs_state(state->pctx, state->shaders[MESA_SHADER_VERTEX]->shader_cso);
break;
case VK_SHADER_STAGE_GEOMETRY_BIT:
state->inlines_dirty[MESA_SHADER_GEOMETRY] = state->shaders[MESA_SHADER_GEOMETRY]->inlines.can_inline;
if (!state->shaders[MESA_SHADER_GEOMETRY]->inlines.can_inline)
state->pctx->bind_gs_state(state->pctx, state->shaders[MESA_SHADER_GEOMETRY]->shader_cso);
state->pctx->bind_gs_state(state->pctx, state->shaders[MESA_SHADER_GEOMETRY]->shader_cso);
state->gs_output_lines = state->shaders[MESA_SHADER_GEOMETRY]->pipeline_nir->nir->info.gs.output_primitive == MESA_PRIM_LINES ? GS_OUTPUT_LINES : GS_OUTPUT_NOT_LINES;
break;
case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
state->inlines_dirty[MESA_SHADER_TESS_CTRL] = state->shaders[MESA_SHADER_TESS_CTRL]->inlines.can_inline;
if (!state->shaders[MESA_SHADER_TESS_CTRL]->inlines.can_inline)
state->pctx->bind_tcs_state(state->pctx, state->shaders[MESA_SHADER_TESS_CTRL]->shader_cso);
state->pctx->bind_tcs_state(state->pctx, state->shaders[MESA_SHADER_TESS_CTRL]->shader_cso);
break;
case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
state->inlines_dirty[MESA_SHADER_TESS_EVAL] = state->shaders[MESA_SHADER_TESS_EVAL]->inlines.can_inline;
state->tess_states[0] = NULL;
state->tess_states[1] = NULL;
if (!state->shaders[MESA_SHADER_TESS_EVAL]->inlines.can_inline) {
if (dynamic_tess_origin) {
state->tess_states[0] = state->shaders[MESA_SHADER_TESS_EVAL]->shader_cso;
state->tess_states[1] = state->shaders[MESA_SHADER_TESS_EVAL]->tess_ccw_cso;
state->pctx->bind_tes_state(state->pctx, state->tess_states[state->tess_ccw]);
} else {
state->pctx->bind_tes_state(state->pctx, state->shaders[MESA_SHADER_TESS_EVAL]->shader_cso);
}
if (dynamic_tess_origin) {
state->tess_states[0] = state->shaders[MESA_SHADER_TESS_EVAL]->shader_cso;
state->tess_states[1] = state->shaders[MESA_SHADER_TESS_EVAL]->tess_ccw_cso;
state->pctx->bind_tes_state(state->pctx, state->tess_states[state->tess_ccw]);
} else {
state->pctx->bind_tes_state(state->pctx, state->shaders[MESA_SHADER_TESS_EVAL]->shader_cso);
}
if (!dynamic_tess_origin)
state->tess_ccw = false;
break;
case VK_SHADER_STAGE_TASK_BIT_EXT:
state->inlines_dirty[MESA_SHADER_TASK] = state->shaders[MESA_SHADER_TASK]->inlines.can_inline;
if (!state->shaders[MESA_SHADER_TASK]->inlines.can_inline)
state->pctx->bind_ts_state(state->pctx, state->shaders[MESA_SHADER_TASK]->shader_cso);
state->pctx->bind_ts_state(state->pctx, state->shaders[MESA_SHADER_TASK]->shader_cso);
break;
case VK_SHADER_STAGE_MESH_BIT_EXT:
state->inlines_dirty[MESA_SHADER_MESH] = state->shaders[MESA_SHADER_MESH]->inlines.can_inline;
if (!state->shaders[MESA_SHADER_MESH]->inlines.can_inline)
state->pctx->bind_ms_state(state->pctx, state->shaders[MESA_SHADER_MESH]->shader_cso);
state->pctx->bind_ms_state(state->pctx, state->shaders[MESA_SHADER_MESH]->shader_cso);
break;
default:
assert(0);
@ -2894,14 +2778,6 @@ static void handle_push_constants(struct vk_cmd_queue_entry *cmd,
state->pcbuf_dirty[MESA_SHADER_TASK] |= (stage_flags & VK_SHADER_STAGE_TASK_BIT_EXT) > 0;
state->pcbuf_dirty[MESA_SHADER_MESH] |= (stage_flags & VK_SHADER_STAGE_MESH_BIT_EXT) > 0;
state->pcbuf_dirty[MESA_SHADER_RAYGEN] |= (stage_flags & LVP_RAY_TRACING_STAGES) > 0;
state->inlines_dirty[MESA_SHADER_VERTEX] |= (stage_flags & VK_SHADER_STAGE_VERTEX_BIT) > 0;
state->inlines_dirty[MESA_SHADER_FRAGMENT] |= (stage_flags & VK_SHADER_STAGE_FRAGMENT_BIT) > 0;
state->inlines_dirty[MESA_SHADER_GEOMETRY] |= (stage_flags & VK_SHADER_STAGE_GEOMETRY_BIT) > 0;
state->inlines_dirty[MESA_SHADER_TESS_CTRL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) > 0;
state->inlines_dirty[MESA_SHADER_TESS_EVAL] |= (stage_flags & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) > 0;
state->inlines_dirty[MESA_SHADER_COMPUTE] |= (stage_flags & VK_SHADER_STAGE_COMPUTE_BIT) > 0;
state->inlines_dirty[MESA_SHADER_TASK] |= (stage_flags & VK_SHADER_STAGE_TASK_BIT_EXT) > 0;
state->inlines_dirty[MESA_SHADER_MESH] |= (stage_flags & VK_SHADER_STAGE_MESH_BIT_EXT) > 0;
}
static void lvp_execute_cmd_buffer(struct list_head *cmds,

259
src/gallium/frontends/lavapipe/lvp_inline_uniforms.c
View file

@ -1,259 +0,0 @@
/*
* Copyright © 2020 Advanced Micro Devices, Inc.
* Copyright © 2022 Valve Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
/* enhanced version of nir_inline_uniforms that can inline from any uniform buffer
* see nir_inline_uniforms.c for more details
*/
#include "nir_builder.h"
#include "nir_loop_analyze.h"
#include "lvp_private.h"
static bool
is_src_uniform_load(nir_src src)
{
if (nir_src_bit_size(src) != 32 || nir_src_num_components(src) != 1 || nir_src_is_const(src))
return false;
return nir_collect_src_uniforms(&src, 0, NULL, NULL,
PIPE_MAX_CONSTANT_BUFFERS, UINT_MAX);
}
static void
process_node(nir_cf_node *node, nir_loop_info *info,
uint32_t *uni_offsets, uint8_t *num_offsets,
struct set *stores)
{
switch (node->type) {
case nir_cf_node_if: {
nir_if *if_node = nir_cf_node_as_if(node);
const nir_src *cond = &if_node->condition;
nir_add_inlinable_uniforms(cond, info, uni_offsets, num_offsets,
PIPE_MAX_CONSTANT_BUFFERS, UINT_MAX);
/* Do not pass loop info down so only alow induction variable
* in loop terminator "if":
*
* for (i = 0; true; i++)
* if (i == count)
* if (i == num)
* <no break>
* break
*
* so "num" won't be inlined due to the "if" is not a
* terminator.
*/
info = NULL;
foreach_list_typed(nir_cf_node, nested_node, node, &if_node->then_list)
process_node(nested_node, info, uni_offsets, num_offsets, stores);
foreach_list_typed(nir_cf_node, nested_node, node, &if_node->else_list)
process_node(nested_node, info, uni_offsets, num_offsets, stores);
break;
}
case nir_cf_node_loop: {
nir_loop *loop = nir_cf_node_as_loop(node);
/* Replace loop info, no nested loop info currently:
*
* for (i = 0; i < count0; i++)
* for (j = 0; j < count1; j++)
* if (i == num)
*
* so "num" won't be inlined due to "i" is an induction
* variable of upper loop.
*/
info = loop->info;
foreach_list_typed(nir_cf_node, nested_node, node, &loop->body) {
bool is_terminator = false;
list_for_each_entry(nir_loop_terminator, terminator,
&info->loop_terminator_list,
loop_terminator_link) {
if (nested_node == &terminator->nif->cf_node) {
is_terminator = true;
break;
}
}
/* Allow induction variables for terminator "if" only:
*
* for (i = 0; i < count; i++)
* if (i == num)
* <no break>
*
* so "num" won't be inlined due to the "if" is not a
* terminator.
*/
nir_loop_info *use_info = is_terminator ? info : NULL;
process_node(nested_node, use_info, uni_offsets, num_offsets, stores);
}
break;
}
case nir_cf_node_block: {
nir_block *block = nir_cf_node_as_block(node);
nir_foreach_instr(instr, block) {
if (instr->type == nir_instr_type_intrinsic) {
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
if (intr->intrinsic == nir_intrinsic_store_deref && is_src_uniform_load(intr->src[1]))
_mesa_set_add(stores, &intr->src[1]);
}
}
break;
}
default:
break;
}
}
bool
lvp_find_inlinable_uniforms(struct lvp_shader *shader, nir_shader *nir)
{
bool ret = false;
struct set *stores = _mesa_set_create(nir, _mesa_hash_pointer, _mesa_key_pointer_equal);
nir_foreach_function_impl(impl, nir) {
nir_metadata_require(impl, nir_metadata_loop_analysis, nir_var_all);
foreach_list_typed(nir_cf_node, node, node, &impl->body)
process_node(node, NULL, (uint32_t*)shader->inlines.uniform_offsets, shader->inlines.count, stores);
}
const unsigned threshold = 5;
set_foreach(stores, entry) {
const nir_src *src = entry->key;
unsigned counter = 0;
list_for_each_entry(nir_src, rsrc, &src->ssa->uses, use_link) {
counter++;
if (counter >= threshold)
break;
}
if (counter >= threshold) {
uint8_t new_num[PIPE_MAX_CONSTANT_BUFFERS];
memcpy(new_num, shader->inlines.count, sizeof(new_num));
uint32_t *uni_offsets =
(uint32_t *) shader->inlines.uniform_offsets;
if (nir_collect_src_uniforms(src, 0, uni_offsets, new_num,
PIPE_MAX_CONSTANT_BUFFERS, UINT_MAX)) {
ret = true;
memcpy(shader->inlines.count, new_num, sizeof(new_num));
}
}
}
for (unsigned i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
if (shader->inlines.count[i]) {
shader->inlines.can_inline |= BITFIELD_BIT(i);
break;
}
}
return ret;
}
void
lvp_inline_uniforms(nir_shader *nir, const struct lvp_shader *shader, const uint32_t *uniform_values, uint32_t ubo)
{
if (!shader->inlines.can_inline)
return;
nir_foreach_function_impl(impl, nir) {
nir_builder b = nir_builder_create(impl);
nir_foreach_block(block, impl) {
nir_foreach_instr_safe(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
/* Only replace loads with constant offsets. */
if (intr->intrinsic == nir_intrinsic_load_ubo &&
nir_src_is_const(intr->src[0]) &&
nir_src_as_uint(intr->src[0]) == ubo &&
nir_src_is_const(intr->src[1]) &&
/* TODO: Can't handle other bit sizes for now. */
intr->def.bit_size == 32) {
int num_components = intr->def.num_components;
uint32_t offset = nir_src_as_uint(intr->src[1]);
const unsigned num_uniforms = shader->inlines.count[ubo];
const unsigned *uniform_dw_offsets = shader->inlines.uniform_offsets[ubo];
if (num_components == 1) {
/* Just replace the uniform load to constant load. */
for (unsigned i = 0; i < num_uniforms; i++) {
if (offset == uniform_dw_offsets[i]) {
b.cursor = nir_before_instr(&intr->instr);
nir_def *def = nir_imm_int(&b, uniform_values[i]);
nir_def_replace(&intr->def, def);
break;
}
}
} else {
/* Lower vector uniform load to scalar and replace each
* found component load with constant load.
*/
uint32_t max_offset = offset + num_components;
nir_def *components[NIR_MAX_VEC_COMPONENTS] = {0};
bool found = false;
b.cursor = nir_before_instr(&intr->instr);
/* Find component to replace. */
for (unsigned i = 0; i < num_uniforms; i++) {
uint32_t uni_offset = uniform_dw_offsets[i];
if (uni_offset >= offset && uni_offset < max_offset) {
int index = uni_offset - offset;
components[index] = nir_imm_int(&b, uniform_values[i]);
found = true;
}
}
if (!found)
continue;
/* Create per-component uniform load. */
for (unsigned i = 0; i < num_components; i++) {
if (!components[i]) {
uint32_t scalar_offset = (offset + i) * 4;
components[i] = nir_load_ubo(&b, 1, intr->def.bit_size,
intr->src[0].ssa,
nir_imm_int(&b, scalar_offset));
nir_intrinsic_instr *load =
nir_instr_as_intrinsic(components[i]->parent_instr);
nir_intrinsic_set_align(load, NIR_ALIGN_MUL_MAX, scalar_offset);
nir_intrinsic_set_range_base(load, scalar_offset);
nir_intrinsic_set_range(load, 4);
}
}
/* Replace the original uniform load. */
nir_def_replace(&intr->def,
nir_vec(&b, components, num_components));
}
}
}
}
nir_metadata_preserve(impl, nir_metadata_control_flow);
}
}

41
src/gallium/frontends/lavapipe/lvp_pipeline.c
View file

@ -62,13 +62,6 @@ shader_destroy(struct lvp_device *device, struct lvp_shader *shader, bool locked
if (!locked)
simple_mtx_lock(&device->queue.lock);
set_foreach(&shader->inlines.variants, entry) {
struct lvp_inline_variant *variant = (void*)entry->key;
destroy[stage](device->queue.ctx, variant->cso);
free(variant);
}
ralloc_free(shader->inlines.variants.table);
if (shader->shader_cso)
destroy[stage](device->queue.ctx, shader->shader_cso);
if (shader->tess_ccw_cso)
@ -322,18 +315,6 @@ compile_spirv(struct lvp_device *pdevice,
return result;
}
static bool
inline_variant_equals(const void *a, const void *b)
{
const struct lvp_inline_variant *av = a, *bv = b;
assert(av->mask == bv->mask);
u_foreach_bit(slot, av->mask) {
if (memcmp(av->vals[slot], bv->vals[slot], sizeof(av->vals[slot])))
return false;
}
return true;
}
static const struct vk_ycbcr_conversion_state *
lvp_ycbcr_conversion_lookup(const void *data, uint32_t set, uint32_t binding, uint32_t array_index)
{
@ -494,12 +475,7 @@ lvp_spirv_to_nir(struct lvp_pipeline *pipeline, const void *pipeline_pNext,
void
lvp_shader_init(struct lvp_shader *shader, nir_shader *nir)
{
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
if (impl->ssa_alloc > 100) //skip for small shaders
shader->inlines.must_inline = lvp_find_inlinable_uniforms(shader, nir);
shader->pipeline_nir = lvp_create_pipeline_nir(nir);
if (shader->inlines.can_inline)
_mesa_set_init(&shader->inlines.variants, NULL, NULL, inline_variant_equals);
}
static VkResult
@ -769,8 +745,6 @@ copy_shader_sanitized(struct lvp_shader *dst, const struct lvp_shader *src)
dst->tess_ccw = NULL; //this gets handled later
assert(!dst->shader_cso);
assert(!dst->tess_ccw_cso);
if (src->inlines.can_inline)
_mesa_set_init(&dst->inlines.variants, NULL, NULL, inline_variant_equals);
}
static VkResult
@ -954,13 +928,11 @@ lvp_pipeline_shaders_compile(struct lvp_pipeline *pipeline, bool locked)
gl_shader_stage stage = i;
assert(stage == pipeline->shaders[i].pipeline_nir->nir->info.stage);
if (!pipeline->shaders[stage].inlines.can_inline) {
pipeline->shaders[stage].shader_cso = lvp_shader_compile(pipeline->device, &pipeline->shaders[stage],
nir_shader_clone(NULL, pipeline->shaders[stage].pipeline_nir->nir), locked);
if (pipeline->shaders[MESA_SHADER_TESS_EVAL].tess_ccw)
pipeline->shaders[MESA_SHADER_TESS_EVAL].tess_ccw_cso = lvp_shader_compile(pipeline->device, &pipeline->shaders[stage],
nir_shader_clone(NULL, pipeline->shaders[MESA_SHADER_TESS_EVAL].tess_ccw->nir), locked);
}
pipeline->shaders[stage].shader_cso = lvp_shader_compile(pipeline->device, &pipeline->shaders[stage],
nir_shader_clone(NULL, pipeline->shaders[stage].pipeline_nir->nir), locked);
if (pipeline->shaders[MESA_SHADER_TESS_EVAL].tess_ccw)
pipeline->shaders[MESA_SHADER_TESS_EVAL].tess_ccw_cso = lvp_shader_compile(pipeline->device, &pipeline->shaders[stage],
nir_shader_clone(NULL, pipeline->shaders[MESA_SHADER_TESS_EVAL].tess_ccw->nir), locked);
}
pipeline->compiled = true;
}
@ -1064,8 +1036,7 @@ lvp_compute_pipeline_init(struct lvp_pipeline *pipeline,
return result;
struct lvp_shader *shader = &pipeline->shaders[MESA_SHADER_COMPUTE];
if (!shader->inlines.can_inline)
shader->shader_cso = lvp_shader_compile(pipeline->device, shader, nir_shader_clone(NULL, shader->pipeline_nir->nir), false);
shader->shader_cso = lvp_shader_compile(pipeline->device, shader, nir_shader_clone(NULL, shader->pipeline_nir->nir), false);
pipeline->compiled = true;
if (pipeline->layout)
shader->push_constant_size = pipeline->layout->push_constant_size;

18
src/gallium/frontends/lavapipe/lvp_private.h
View file

@ -439,12 +439,6 @@ lvp_pipeline_nir_ref(struct lvp_pipeline_nir **dst, struct lvp_pipeline_nir *src
*dst = src;
}
struct lvp_inline_variant {
uint32_t mask;
uint32_t vals[PIPE_MAX_CONSTANT_BUFFERS][MAX_INLINABLE_UNIFORMS];
void *cso;
};
struct lvp_shader {
struct vk_object_base base;
struct lvp_pipeline_layout *layout;
@ -452,13 +446,6 @@ struct lvp_shader {
struct lvp_pipeline_nir *tess_ccw;
void *shader_cso;
void *tess_ccw_cso;
struct {
uint32_t uniform_offsets[PIPE_MAX_CONSTANT_BUFFERS][MAX_INLINABLE_UNIFORMS];
uint8_t count[PIPE_MAX_CONSTANT_BUFFERS];
bool must_inline;
uint32_t can_inline; //bitmask
struct set variants;
} inlines;
struct pipe_stream_output_info stream_output;
struct blob blob; //preserved for GetShaderBinaryDataEXT
uint32_t push_constant_size;
@ -812,10 +799,7 @@ lvp_shader_init(struct lvp_shader *shader, nir_shader *nir);
void
lvp_shader_optimize(nir_shader *nir);
bool
lvp_find_inlinable_uniforms(struct lvp_shader *shader, nir_shader *nir);
void
lvp_inline_uniforms(nir_shader *nir, const struct lvp_shader *shader, const uint32_t *uniform_values, uint32_t ubo);
void *
lvp_shader_compile(struct lvp_device *device, struct lvp_shader *shader, nir_shader *nir, bool locked);

1
src/gallium/frontends/lavapipe/meson.build
View file

@ -28,7 +28,6 @@ liblvp_files = files(
'lvp_util.c',
'lvp_image.c',
'lvp_formats.c',
'lvp_inline_uniforms.c',
'lvp_pipe_sync.c',
'lvp_pipeline.c',
'lvp_pipeline_cache.c',