Commit graph

172883 commits

Author SHA1 Message Date
Dmitry Baryshkov
f50da71198 freedreno/registers: fix WB doffsets array in mdp5.xml
In mdp5.xml the doffsets attribute of the WB array contains one extra
comma, resulting in one empty entry in __offset_WB(). Fix that now.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28193>
2024-03-22 19:30:05 +00:00
Dmitry Baryshkov
7f2af6841b freedreno/registers: inline mdp4_csc group
The gen_headers.py script doesn't support and is not going to support
group declarations. Inline the only user of group / use-group
definitions, mdp4_csc.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28193>
2024-03-22 19:30:05 +00:00
Dmitry Baryshkov
a3d8acc875 freedreno/registers: add missing copyright imports
Import copyright into all files so that it is included into the
generated headers.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28193>
2024-03-22 19:30:05 +00:00
Dmitry Baryshkov
bf89f777f8 freedreno/registers: fix generation dependencies
The rules-ng.xsd is not a registers XML file, don't pass it to
gen_header.py. Instead declare rules-ng.xsd and freedreno_copyright.xml
as inputs to the gen_header.py, so that the headers are regenerated if
schema or copyright file changes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28193>
2024-03-22 19:30:05 +00:00
Samuel Pitoiset
2ab3a5a0f7 zink/ci: allow RADV_PERFTEST=shader_object on NAVI31
NAVI10/VANGOGH are waiting for another fix related to NGG culling
for passing CI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28338>
2024-03-22 19:05:41 +00:00
Yonggang Luo
1d18aba016 meson: Remove the non-used -DDEBUG manually
And also remove the workarounds for LLVM and bellagio

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28092>
2024-03-22 18:22:34 +00:00
Yonggang Luo
1ac1c0843f treewide: Replace usage of macro DEBUG with MESA_DEBUG when possible
This is achieved by the following steps:

#ifndef DEBUG => #if !MESA_DEBUG
defined(DEBUG) => MESA_DEBUG
#ifdef DEBUG => #if MESA_DEBUG

This is done by replace in vscode

excludes
docs,*.rs,addrlib,src/imgui,*.sh,src/intel/vulkan/grl/gpu

These are safe because those files should keep DEBUG macro is already excluded;
and not directly replace DEBUG, as we have some symbols around it.

Use debug or NDEBUG instead of DEBUG in comments when proper

This for reduce the usage of DEBUG,
so it's easier migrating to MESA_DEBUG

These are found when migrating DEBUG to MESA_DEBUG,
these are all comment update, so it's safe

Replace comment /* DEBUG */ and /* !DEBUG */ with proper /* MESA_DEBUG */ or /* !MESA_DEBUG */ manually

DEBUG || !NDEBUG -> MESA_DEBUG || !NDEBUG
!DEBUG && NDEBUG -> !(MESA_DEBUG || !NDEBUG)

Replace the DEBUG present in comment with proper new MESA_DEBUG manually

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28092>
2024-03-22 18:22:34 +00:00
Matthew Waters
cf8f894921 teximage: allow glCopyTex{Sub}Image[123]D into R/RG textures with OpenGL ES 2.0
This is explicitly allowed in the GL_EXT_texture_rg extension.

Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28313>
2024-03-22 17:04:55 +00:00
Jesse Natalie
63366781aa wgl: Check for null before dereferencing ctx in swap
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28211>
2024-03-22 16:40:08 +00:00
Jesse Natalie
df638c023d wgl: Delete unused context param to swap
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28211>
2024-03-22 16:40:08 +00:00
Samuel Pitoiset
f729fe50e5 radv: trigger a new PS epilog when the framebuffer is dirty with ESO
When a new framebuffer is used, the color output formats might have
changed and a new PS epilog might need to be recompiled. This shouldn't
affect graphics pipeline because color output formats must already match.

This fixes a couple of failures/flakes like
spec@ext_framebuffer_multisample@fast-clear with Zink and shader object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28294>
2024-03-22 15:08:23 +00:00
Samuel Pitoiset
53ec57d42d radv: always export MRTZ in FS epilogs with ESO on GFX11
Alpha to coverage is special on RDNA3 and it needs to be emitted
through MRTZ in some situations. Because we can't know this at compile
time when everything is dynamic, we have to always emit MRTZ in PS
epilogs.

This fixes remaining failures on NAVI31 with Zink/ESO/RADV like
spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-drawpixels-float-and-ushort.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28297>
2024-03-22 14:42:21 +00:00
Hans-Kristian Arntzen
1900617baf wsi/wayland: Init outstanding list earlier.
Fixes a crash if swapchain free is called before the list is
initialized. This only happens when swapchain init fails, so
it is highly unlikely to happen in practical scenarios.

Fixes dEQP-VK.wsi.wayland.swapchain.simulate_oom.min_image_count.

Fixes: 0d51cd4808 ("wsi/wl: Improve fallback for present_wait.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10866

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Tested-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28325>
2024-03-22 14:02:26 +00:00
duncan.hopkins
f75750f740 zink/apple: added moltenvk-dir search to allow MoltenVK to be sourced from brew.
The file layout in the brew obtained molten-vk package is differnt again to the VulkanSDK or MoltenVK packages.
Added an extra sub-directory location search from the `moltenvk-dir` build option.

This allows for the following to be used `-Dmoltenvk-dir=$(brew --prefix molten-vk)`.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28330>
2024-03-22 11:56:01 +00:00
Thomas H.P. Andersen
5532f13566 driconf: override vendor id for X4 Foundations on NVK
The game will refuse to start if the driver version is tool old.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27784>
2024-03-22 11:18:55 +00:00
Thomas H.P. Andersen
03d72c4ef1 nvk: support driconf option force_vk_vendor
Some games match on the vendor ID and then check if the driver version
is at least a specific version. Some games just warn about the "old" driver
version. Others refuse to start.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27784>
2024-03-22 11:18:55 +00:00
Eric Engestrom
951aa2fa82 v3dv/ci: add other flakes seen during nightly run
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28333>
2024-03-22 10:58:35 +00:00
Eric Engestrom
423e85caf5 v3dv/ci: mark the dEQP-VK.wsi.*.maintenance1.deferred_alloc.* flakes seen so far as happening on all platforms
Not all of these have flaked on all platforms yet, but enough that it's
safer to just consider that alloc issues might not be platform-specific.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28333>
2024-03-22 10:58:35 +00:00
Eric Engestrom
648490f7ce vc4/ci: add another spec@arb_vertex_buffer_object@vbo-subdata-many draw flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28333>
2024-03-22 10:58:35 +00:00
Eric Engestrom
5f2915e8ee vc4/ci: add another spec@!opengl 1.1@depthstencil-default_fb-drawpixels flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28333>
2024-03-22 10:58:35 +00:00
Eric Engestrom
fa0f834453 v3d/ci: mark spec@ext_framebuffer_blit@fbo-blit-check-limits as fixed
It looks like it has been fixed for many drivers yesterday, but
apparently not vc4.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28333>
2024-03-22 10:58:35 +00:00
Rhys Perry
588b1ce533 aco: split instruction assembly into functions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
5651aa7644 aco/gfx11: fix scratch ST mode assembly
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
cdcc856cbf aco: unify MIMG opcode lists
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
20b14381c4 aco: move dot/wmma instructions into VOP3P list
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
6bfd3dc39f aco: use op()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
a806e48982 aco: use single tuple for all opcode numbers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
5864c22fb7 aco: refactor VOPC opcode list
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
d23f8b0dcf aco: rename opcode->instruction
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
Rhys Perry
b723a15bd0 aco: fix GFX6 buffer_load_dwordx4 opcode number
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
2024-03-22 10:29:43 +00:00
David Heidelberg
cb17a936e0 ci/r300: implement rules for d3d9 testing
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Suggested-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28305>
2024-03-22 10:38:04 +01:00
Pierre-Eric Pelloux-Prayer
9c909aefc4 amd: fix addrlib regression
This reverts only a small chunk of e01266335b because this
change caused this piglit test to page fault:

   nv_copy_image-formats --samples=8 GL_RGB32UI

Fixes: e01266335b ("amd: update addrlib")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28268>
2024-03-22 08:25:21 +00:00
Pierre-Eric Pelloux-Prayer
53f9cdac9b radeonsi: preserve alpha if needed in kill_ps_outputs_cb
Some features (eg: ALPHA_TEST) relies on the alpha value being
exported even if color_mask.a = false.

In these cases, override comp_mask to preserve the alpha value.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10841
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10845
Fixes: 6d2a7f53 ("radeonsi: decrease NUM_INTERP if export formats/colormask eliminated PS inputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28268>
2024-03-22 08:25:21 +00:00
Mark Janes
4acea392af intel/compiler: drop unused ray-tracing fields from cache hash
The compiler only references `intel_device_info->subslice_masks` for
ray tracing workloads.  Platforms which lack raytracing support can
share a cache even if they differ on this field.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28311>
2024-03-22 00:01:28 +00:00
Kenneth Graunke
9a72116367 intel/brw: Unify DF and Q/UQ lowering for MOV
Using the new unsupported_64bit_type helper.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Kenneth Graunke
97c7d5113d intel/brw: Use correct execution pipe for lowering SEL on DF
This is a float operation, let's keep it on the float pipe.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Kenneth Graunke
26d65e96dd intel/brw: Assert that min/max are not happening in 64-bit SEL lowering
These aren't handled, only pure selects.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Kenneth Graunke
a2c2a7bc00 intel/brw: Fix check for 64-bit SEL lowering types
The 64-bit type lowering for SEL in opt_algebraic had a pre-existing bug
where it only triggered when 64-bit float _and_ integer types were
unsupported.  Meteorlake supports 64-bit float but not integer, so we
need to lower Q/UQ in that case still.

When I moved this to a later pass, opt_peephole_sel started generating
Q/UQ SEL instructions which were failing to be lowered.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10867
Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Dylan Baker
75ede9d9bc intel/brw: track last successful pass and leave the loop early
This is similar to what RADV implements using the NIR_LOOP_PASS
helpers. I have not used those helpers for a couple of reasons:

 1. They use the pointer to the optimization function, which doesn't
    work if the same function is called multiple times in one invocation
    of the loop (fixable)
 2. After fixing them, due to Intel's use of sub-expressions, the amount
    of code added to wrap the shared macro becomes more than simply
    reimplementing them for the Intel compiler

On most workloads the results are a wash, but on compile heavy
workloads like Cyberpunk 2077 and Rise of the Tomb Raider, I saw
fossil-db runtimes fall by 1-2% on my ICL, with no changes to the
compiled shaders. Caio saw closer to 2.5% on TGL.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27510>
2024-03-21 23:02:32 +00:00
Caio Oliveira
b2ee98d2db intel/brw: Handle Xe2 in brw_fs_opt_zero_samples
The mlen tracking is in REG_SIZE units, but in Xe2 each GRF has
doubled the size.  The optimization can only elide full GRFs, so
round down the amount of trailing zeros to ensure the optimization
will remove only full GRFs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28279>
2024-03-21 22:38:54 +00:00
Ian Romanick
cd70e49394 intel/brw: Allow SIMD16 F and HF type conversion moves
On DG2, the lowering generated for these MOV instructions is
**awful**. The original SIMD16 MOV

    { 18}   67: mov(16) vgrf54+0.0:HF, vgrf46+0.0:F NoMask group0

is lowered to SIMD8 MOVs:

    { 18}  118: mov(8) vgrf54+0.0:HF, vgrf46+0.0:F NoMask group0
    { 18}  119: mov(8) vgrf54+0.16:HF, vgrf46+1.0:F NoMask group8

These MOVs violate Gfx12.5 region restrictions, so these are further
lowered:

    { 17}  119: mov(8) vgrf83<2>:HF, vgrf46+0.0:F NoMask group0
    { 19}  120: mov(8) vgrf54+0.0:UW, vgrf83<2>:UW NoMask group0
    { 19}  122: mov(8) vgrf84<2>:HF, vgrf46+1.0:F NoMask group8
    { 19}  123: mov(8) vgrf54+0.16:UW, vgrf84<2>:UW NoMask group8

The shader-db and fossil-db results are nothing to get excited
about. However, the affect on vk_cooperative_matrix_perf is substantial. In one subtest

shader: shaders/shmemfp16.spv

cooperativeMatrixProps = 8x8x16   A = float16_t B = float16_t C = float16_t D = float16_t scope = subgroup
TILE_M=128 TILE_N=128, TILE_K=32 BLayout=0

performance on my DG2 improved by ~60% due to a MASSIVE reduction in spills and fills:

-Native code for unnamed compute shader (null) (src_hash 0x00000000) (sha1 c6a41b1c4e7aa2da327a39a70ed36c822a4b172f)
-SIMD32 shader: 32484 instructions. 1 loops. 1893868 cycles. 737:1820 spills:fills, 442 sends, scheduled with mode none. Promoted 1 constants. Compacted 519744 to 492224 bytes (5%)
-   START B0 (20782 cycles)
+Native code for unnamed compute shader (null) (src_hash 0x00000000) (sha1 621e960daad5b5579b176717f24a315e7ea560a1)
+SIMD32 shader: 23918 instructions. 1 loops. 1089894 cycles. 432:1166 spills:fills, 442 sends, scheduled with mode none. Promoted 1 constants. Compacted 382688 to 353232 bytes (8%)

shader-db:

All Gfx9 and later platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19656270 -> 19653981 (-0.01%)
instructions in affected programs: 61810 -> 59521 (-3.70%)
helped: 116 / HURT: 0

total cycles in shared programs: 823368888 -> 823375854 (<.01%)
cycles in affected programs: 1165284 -> 1172250 (0.60%)
helped: 51 / HURT: 57

fossil-db:

DG2 and Meteor Lake had similar results. (Meteor Lake shown)
*** Shaders only in 'before' results are ignored:
fossil-db/steam-dxvk/total_war_warhammer3/2a3ed2ca632a7cb7/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/18b9d4a3b1961616/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/04ac9f3146a6db19/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/f37ebec6aa1b379a/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/255c987feb0d4310/fs.32, and 25
more
from 1 apps: fossil-db/steam-dxvk/total_war_warhammer3

Totals:
Instrs: 160946537 -> 160928389 (-0.01%); split: -0.01%, +0.00%
Cycles: 14125908620 -> 14125873958 (-0.00%); split: -0.00%, +0.00%

Totals from 1002 (0.15% of 652134) affected shaders:
Instrs: 411261 -> 393113 (-4.41%); split: -4.41%, +0.00%
Cycles: 16676735 -> 16642073 (-0.21%); split: -0.48%, +0.27%

Tiger Lake
Totals:
Instrs: 164511816 -> 164497202 (-0.01%); split: -0.01%, +0.00%
Cycles: 13801675722 -> 13801629397 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 7955168 -> 7955152 (-0.00%)
Send messages: 8544494 -> 8544486 (-0.00%)

Totals from 997 (0.15% of 651454) affected shaders:
Instrs: 460820 -> 446206 (-3.17%); split: -3.17%, +0.00%
Cycles: 16265514 -> 16219189 (-0.28%); split: -0.84%, +0.56%
Subgroup size: 17552 -> 17536 (-0.09%)
Send messages: 26045 -> 26037 (-0.03%)

Ice Lake
Totals:
Instrs: 165504747 -> 165489970 (-0.01%); split: -0.01%, +0.00%
Cycles: 15145244554 -> 15145149627 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 8107032 -> 8107016 (-0.00%)
Send messages: 8598680 -> 8598672 (-0.00%)
Spill count: 45427 -> 45423 (-0.01%)
Fill count: 74749 -> 74747 (-0.00%)

Totals from 1125 (0.17% of 656115) affected shaders:
Instrs: 521676 -> 506899 (-2.83%); split: -2.83%, +0.00%
Cycles: 19555434 -> 19460507 (-0.49%); split: -0.59%, +0.10%
Subgroup size: 21616 -> 21600 (-0.07%)
Send messages: 28623 -> 28615 (-0.03%)
Spill count: 603 -> 599 (-0.66%)
Fill count: 1362 -> 1360 (-0.15%)

Skylake
*** Shaders only in 'after' results are ignored:
fossil-db/steam-native/red_dead_redemption2/cef460b80bad8485/fs.16,
fossil-db/steam-native/red_dead_redemption2/cd5fe081e2e5529d/fs.16
from 1 apps: fossil-db/steam-native/red_dead_redemption2

Totals:
Instrs: 141607617 -> 141593776 (-0.01%); split: -0.01%, +0.00%
Cycles: 14257812441 -> 14257661671 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 7743752 -> 7743736 (-0.00%)
Send messages: 7552728 -> 7552720 (-0.00%)
Spill count: 43660 -> 43661 (+0.00%)
Fill count: 71301 -> 71303 (+0.00%)

Totals from 1017 (0.16% of 636964) affected shaders:
Instrs: 392454 -> 378613 (-3.53%); split: -3.53%, +0.00%
Cycles: 16622974 -> 16472204 (-0.91%); split: -1.04%, +0.13%
Subgroup size: 19840 -> 19824 (-0.08%)
Send messages: 23021 -> 23013 (-0.03%)
Spill count: 484 -> 485 (+0.21%)
Fill count: 1155 -> 1157 (+0.17%)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28281>
2024-03-21 15:12:58 -07:00
Ian Romanick
66dc6e07f5 intel/brw: Fix handling of accumulator register numbers
Folks, there's more than one accumulator. In general, when the
register file is ARF, the upper 4 bits of the register number specify
which ARF, and the lower 4 bits specify which one of that ARF. This
can be further partitioned by the subregister number.

This is already mostly handled correctly for flags register, but lots
of places wanted to check the register number for equality with
BRW_ARF_ACCUMULATOR. If acc1 is ever specified, that won't work.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28281>
2024-03-21 15:12:54 -07:00
David Heidelberg
d8f53f698c util: move gen_zipped_file into generic util and rename to gen_zipped_xml_file
Make the filename more descriptive and since the file is used by
multiple drivers, move it into appropriate util/ directory.

Cosmetics:
 - use SPDX license tag
 - add newline before main function

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27804>
2024-03-21 20:48:41 +00:00
Echo J
16753bc2f1 nvk: Implement calibrated timestamps
This implementation is mostly a copy-paste from RADV

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28274>
2024-03-21 20:11:49 +00:00
Echo J
4b0ad410d0 nvk: Advertise VK_VALVE_mutable_descriptor_type
This missing extension looks bad when most of the other drivers
have it (so that's why I made this change)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28291>
2024-03-21 19:15:28 +00:00
Faith Ekstrand
359bb89302 nvk: Move the mutableDescriptorType enable
The EXT extension overrides the VALVE one so put it in the EXT section.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28291>
2024-03-21 19:15:28 +00:00
José Roberto de Souza
1bed037b88 iris: Remove i915_drm.h include from iris_indirect_gen.c
It don't use i915_drm.h no need to include.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28327>
2024-03-21 18:52:14 +00:00
José Roberto de Souza
50eceb1e33 iris: Move tiling_to_modifier() implementation to i915 folder
There is no tiling in Xe KMD uAPI.
With this one more i915_drm.h include can be removed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28327>
2024-03-21 18:52:14 +00:00
Rohan Garg
cc570dbada isl: enable CCS for 3D surfaces on gen12.5 and above
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23632>
2024-03-21 18:28:27 +00:00
Rohan Garg
49ed35c08a anv: 3D surfaces have fewer layers for higher miplevels
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23632>
2024-03-21 18:28:27 +00:00