intel/brw: Fix check for 64-bit SEL lowering types

The 64-bit type lowering for SEL in opt_algebraic had a pre-existing bug
where it only triggered when 64-bit float _and_ integer types were
unsupported.  Meteorlake supports 64-bit float but not integer, so we
need to lower Q/UQ in that case still.

When I moved this to a later pass, opt_peephole_sel started generating
Q/UQ SEL instructions which were failing to be lowered.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10867
Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
This commit is contained in:
Kenneth Graunke 2024-03-21 10:58:20 -07:00 committed by Marge Bot
parent 75ede9d9bc
commit a2c2a7bc00

View file

@ -562,6 +562,15 @@ brw_fs_lower_3src_null_dest(fs_visitor &s)
return progress;
}
static bool
unsupported_64bit_type(const intel_device_info *devinfo,
enum brw_reg_type type)
{
return (!devinfo->has_64bit_float && type == BRW_REGISTER_TYPE_DF) ||
(!devinfo->has_64bit_int && (type == BRW_REGISTER_TYPE_UQ ||
type == BRW_REGISTER_TYPE_Q));
}
/**
* Perform lowering to legalize the IR for various ALU restrictions.
*
@ -620,11 +629,7 @@ brw_fs_lower_alu_restrictions(fs_visitor &s)
break;
case BRW_OPCODE_SEL:
if (!devinfo->has_64bit_float &&
!devinfo->has_64bit_int &&
(inst->dst.type == BRW_REGISTER_TYPE_DF ||
inst->dst.type == BRW_REGISTER_TYPE_UQ ||
inst->dst.type == BRW_REGISTER_TYPE_Q)) {
if (unsupported_64bit_type(devinfo, inst->dst.type)) {
assert(inst->dst.type == inst->src[0].type);
assert(!inst->saturate);
assert(!inst->src[0].abs && !inst->src[0].negate);