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aco: rename opcode->instruction
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
This commit is contained in:
Rhys Perry
Marge Bot
parent
b723a15bd0
commit
d23f8b0dcf
4 changed files with 152 additions and 152 deletions
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@ -675,7 +675,7 @@ void hw_init_scratch(Builder& bld, Definition def, Operand scratch_addr, Operand
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#endif /* _ACO_BUILDER_ */"""
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from aco_opcodes import opcodes, Format
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from aco_opcodes import Format
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from mako.template import Template
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print(Template(template).render(opcodes=opcodes, Format=Format))
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print(Template(template).render(Format=Format))
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@ -222,7 +222,7 @@ class Format(IntEnum):
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return res
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class Opcode(object):
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class Instruction(object):
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"""Class that represents all the information we have about the opcode
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NOTE: this must be kept in sync with aco_op_info
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"""
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@ -292,51 +292,51 @@ def src(op1 = 0, op2 = 0, op3 = 0, op4 = 0):
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def dst(def1 = 0, def2 = 0, def3 = 0, def4 = 0):
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return def1 | (def2 << 8) | (def3 << 16) | (def4 << 24)
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# global dictionary of opcodes
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opcodes = {}
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# global dictionary of instructions
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instructions = {}
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def opcode(name, opcode_gfx7 = -1, opcode_gfx9 = -1, opcode_gfx10 = -1, opcode_gfx11 = -1, format = Format.PSEUDO, cls = InstrClass.Other, input_mod = False, output_mod = False, is_atomic = False, definitions = 0, operands = 0):
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assert name not in opcodes
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opcodes[name] = Opcode(name, opcode_gfx7, opcode_gfx9, opcode_gfx10, opcode_gfx11, format, input_mod, output_mod, is_atomic, cls, definitions, operands)
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def insn(name, opcode_gfx7 = -1, opcode_gfx9 = -1, opcode_gfx10 = -1, opcode_gfx11 = -1, format = Format.PSEUDO, cls = InstrClass.Other, input_mod = False, output_mod = False, is_atomic = False, definitions = 0, operands = 0):
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assert name not in instructions
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instructions[name] = Instruction(name, opcode_gfx7, opcode_gfx9, opcode_gfx10, opcode_gfx11, format, input_mod, output_mod, is_atomic, cls, definitions, operands)
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def default_class(opcodes, cls):
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for op in opcodes:
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if isinstance(op[-1], InstrClass):
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yield op
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def default_class(instructions, cls):
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for i in instructions:
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if isinstance(i[-1], InstrClass):
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yield i
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else:
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yield op + (cls,)
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yield i + (cls,)
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opcode("exp", 0, 0, 0, 0, format = Format.EXP, cls = InstrClass.Export)
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opcode("p_parallelcopy")
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opcode("p_startpgm")
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opcode("p_return")
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opcode("p_phi")
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opcode("p_linear_phi")
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opcode("p_as_uniform")
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opcode("p_unit_test")
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insn("exp", 0, 0, 0, 0, format = Format.EXP, cls = InstrClass.Export)
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insn("p_parallelcopy")
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insn("p_startpgm")
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insn("p_return")
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insn("p_phi")
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insn("p_linear_phi")
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insn("p_as_uniform")
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insn("p_unit_test")
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opcode("p_create_vector")
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opcode("p_extract_vector")
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opcode("p_split_vector")
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insn("p_create_vector")
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insn("p_extract_vector")
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insn("p_split_vector")
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# start/end the parts where we can use exec based instructions
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# implicitly
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opcode("p_logical_start")
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opcode("p_logical_end")
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insn("p_logical_start")
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insn("p_logical_end")
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# e.g. subgroupMin() in SPIR-V
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opcode("p_reduce", format=Format.PSEUDO_REDUCTION)
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insn("p_reduce", format=Format.PSEUDO_REDUCTION)
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# e.g. subgroupInclusiveMin()
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opcode("p_inclusive_scan", format=Format.PSEUDO_REDUCTION)
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insn("p_inclusive_scan", format=Format.PSEUDO_REDUCTION)
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# e.g. subgroupExclusiveMin()
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opcode("p_exclusive_scan", format=Format.PSEUDO_REDUCTION)
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insn("p_exclusive_scan", format=Format.PSEUDO_REDUCTION)
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opcode("p_branch", format=Format.PSEUDO_BRANCH)
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opcode("p_cbranch", format=Format.PSEUDO_BRANCH)
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opcode("p_cbranch_z", format=Format.PSEUDO_BRANCH)
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opcode("p_cbranch_nz", format=Format.PSEUDO_BRANCH)
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insn("p_branch", format=Format.PSEUDO_BRANCH)
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insn("p_cbranch", format=Format.PSEUDO_BRANCH)
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insn("p_cbranch_z", format=Format.PSEUDO_BRANCH)
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insn("p_cbranch_nz", format=Format.PSEUDO_BRANCH)
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opcode("p_barrier", format=Format.PSEUDO_BARRIER)
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insn("p_barrier", format=Format.PSEUDO_BARRIER)
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# Primitive Ordered Pixel Shading pseudo-instructions.
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@ -350,11 +350,11 @@ opcode("p_barrier", format=Format.PSEUDO_BARRIER)
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# Operands:
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# - s1 value to add, usually -(current_wave_ID + 1) (or ~current_wave_ID) to remap the exiting wave
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# ID from wrapping [0, 0x3FF] to monotonic [0, 0xFFFFFFFF].
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opcode("p_pops_gfx9_add_exiting_wave_id")
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insn("p_pops_gfx9_add_exiting_wave_id")
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# Indicates that the wait for the completion of the ordered section in overlapped waves has been
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# finished on GFX9-10.3. Not lowered to any hardware instructions.
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opcode("p_pops_gfx9_overlapped_wave_wait_done")
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insn("p_pops_gfx9_overlapped_wave_wait_done")
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# Indicates that a POPS ordered section has ended, hints that overlapping waves can possibly
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# continue execution. The overlapping waves may actually be resumed by this instruction or anywhere
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@ -364,65 +364,65 @@ opcode("p_pops_gfx9_overlapped_wave_wait_done")
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# in the program if POPS is used, however, otherwise the location of the end of the ordered section
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# will be undefined. Only needed on GFX9-10.3 (GFX11+ ordered section is until the last export,
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# can't be exited early). Not lowered to any hardware instructions.
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opcode("p_pops_gfx9_ordered_section_done")
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insn("p_pops_gfx9_ordered_section_done")
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opcode("p_spill")
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opcode("p_reload")
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insn("p_spill")
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insn("p_reload")
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# Start/end linear vgprs. p_start_linear_vgpr can take an operand to copy from, into the linear vgpr
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opcode("p_start_linear_vgpr")
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opcode("p_end_linear_vgpr")
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insn("p_start_linear_vgpr")
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insn("p_end_linear_vgpr")
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opcode("p_end_wqm")
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opcode("p_discard_if")
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opcode("p_demote_to_helper")
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opcode("p_is_helper")
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opcode("p_exit_early_if")
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insn("p_end_wqm")
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insn("p_discard_if")
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insn("p_demote_to_helper")
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insn("p_is_helper")
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insn("p_exit_early_if")
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# simulates proper bpermute behavior using v_readlane_b32
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# definitions: result VGPR, temp EXEC, clobbered VCC
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# operands: index, input data
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opcode("p_bpermute_readlane")
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insn("p_bpermute_readlane")
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# simulates proper wave64 bpermute behavior using shared vgprs (for GFX10/10.3)
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# definitions: result VGPR, temp EXEC, clobbered SCC
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# operands: index * 4, input data, same half (bool)
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opcode("p_bpermute_shared_vgpr")
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insn("p_bpermute_shared_vgpr")
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# simulates proper wave64 bpermute behavior using v_permlane64_b32 (for GFX11+)
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# definitions: result VGPR, temp EXEC, clobbered SCC
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# operands: linear VGPR, index * 4, input data, same half (bool)
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opcode("p_bpermute_permlane")
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insn("p_bpermute_permlane")
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# creates a lane mask where only the first active lane is selected
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opcode("p_elect")
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insn("p_elect")
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opcode("p_constaddr")
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opcode("p_resume_shader_address")
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insn("p_constaddr")
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insn("p_resume_shader_address")
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# These don't have to be pseudo-ops, but it makes optimization easier to only
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# have to consider two instructions.
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# (src0 >> (index * bits)) & ((1 << bits) - 1) with optional sign extension
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opcode("p_extract") # src1=index, src2=bits, src3=signext
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insn("p_extract") # src1=index, src2=bits, src3=signext
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# (src0 & ((1 << bits) - 1)) << (index * bits)
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opcode("p_insert") # src1=index, src2=bits
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insn("p_insert") # src1=index, src2=bits
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opcode("p_init_scratch")
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insn("p_init_scratch")
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# jumps to a shader epilog
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opcode("p_jump_to_epilog")
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insn("p_jump_to_epilog")
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# loads and interpolates a fragment shader input with a correct exec mask
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#dst0=result, src0=linear_vgpr, src1=attribute, src2=component, src3=coord1, src4=coord2, src5=m0
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#dst0=result, src0=linear_vgpr, src1=attribute, src2=component, src3=dpp_ctrl, src4=m0
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opcode("p_interp_gfx11")
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insn("p_interp_gfx11")
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# performs dual source MRTs swizzling and emits exports on GFX11
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opcode("p_dual_src_export_gfx11")
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insn("p_dual_src_export_gfx11")
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# Let shader end with specific registers set to wanted value, used by multi part
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# shader to pass arguments to next part.
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opcode("p_end_with_regs")
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insn("p_end_with_regs")
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# SOP2 instructions: 2 scalar inputs, 1 scalar output (+optional scc)
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SOP2 = {
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@ -486,7 +486,7 @@ SOP2 = {
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( -1, -1, -1, -1, -1, -1, "p_resumeaddr_addlo", dst(1, SCC), src(1, 1, 1)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOP2, InstrClass.Salu):
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.SOP2, cls, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOP2, cls, definitions = defs, operands = ops)
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# SOPK instructions: 0 input (+ imm), 1 output + optional scc
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@ -522,7 +522,7 @@ SOPK = {
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( -1, -1, -1, -1, 0x1c, 0x17, "s_subvector_loop_end", dst(), src(), InstrClass.Branch),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOPK, InstrClass.Salu):
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.SOPK, cls, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOPK, cls, definitions = defs, operands = ops)
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# SOP1 instructions: 1 input, 1 output (+optional SCC)
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@ -604,7 +604,7 @@ SOP1 = {
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( -1, -1, -1, -1, -1, -1, "p_load_symbol", dst(1), src(1)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOP1, InstrClass.Salu):
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.SOP1, cls, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOP1, cls, definitions = defs, operands = ops)
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# SOPC instructions: 2 inputs and 0 outputs (+SCC)
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@ -632,7 +632,7 @@ SOPC = {
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( -1, -1, 0x13, 0x13, 0x13, 0x11, "s_cmp_lg_u64", dst(SCC), src(2, 2)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops) in SOPC:
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.SOPC, InstrClass.Salu, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOPC, InstrClass.Salu, definitions = defs, operands = ops)
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# SOPP instructions: 0 inputs (+optional scc/vcc), 0 outputs
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@ -681,7 +681,7 @@ SOPP = {
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( -1, -1, -1, -1, -1, 0x0b, "s_wait_event", dst(), src()),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOPP, InstrClass.Salu):
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.SOPP, cls, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOPP, cls, definitions = defs, operands = ops)
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# SMEM instructions: sbase input (2 sgpr), potentially 2 offset inputs, 1 sdata input/output
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@ -776,7 +776,7 @@ SMEM = {
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( -1, -1, -1, 0xac, 0xac, -1, "s_atomic_dec_x2"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in SMEM:
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.SMEM, InstrClass.SMem, is_atomic = "atomic" in name)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SMEM, InstrClass.SMem, is_atomic = "atomic" in name)
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# VOP2 instructions: 2 inputs, 1 output (+ optional vcc)
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@ -861,7 +861,7 @@ VOP2 = {
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( -1, -1, -1, 0x37, 0x02, 0x02, "v_dot2c_f32_f16", False, False, dst(1), src(1, 1, 1)), #v_dot2acc_f32_f16 in GFX11
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, in_mod, out_mod, defs, ops) in VOP2:
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOP2, InstrClass.Valu32, in_mod, out_mod, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOP2, InstrClass.Valu32, in_mod, out_mod, definitions = defs, operands = ops)
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# VOP1 instructions: instructions with 1 input and 1 output
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@ -966,7 +966,7 @@ VOP1 = {
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( -1, -1, -1, -1, -1, 0x1c, "v_mov_b16", True, False, dst(1), src(1)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, in_mod, out_mod, defs, ops, cls) in default_class(VOP1, InstrClass.Valu32):
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOP1, cls, in_mod, out_mod, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOP1, cls, in_mod, out_mod, definitions = defs, operands = ops)
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# VOPC instructions:
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@ -980,29 +980,29 @@ VOPC_CLASS = {
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(0xb8, 0xb8, 0x13, 0x13, 0xb8, 0xff, "v_cmpx_class_f64", dst(EXEC), src(2, 1), InstrClass.ValuDouble),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(VOPC_CLASS, InstrClass.Valu32):
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, cls, True, False, definitions = defs, operands = ops)
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, cls, True, False, definitions = defs, operands = ops)
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COMPF = ["f", "lt", "eq", "le", "gt", "lg", "ge", "o", "u", "nge", "nlg", "ngt", "nle", "neq", "nlt", "tru"]
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for i in range(8):
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(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0x20+i, 0x20+i, 0xc8+i, 0x00+i, "v_cmp_"+COMPF[i]+"_f16")
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(VCC), operands = src(1, 1))
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(VCC), operands = src(1, 1))
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(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0x30+i, 0x30+i, 0xd8+i, 0x80+i, "v_cmpx_"+COMPF[i]+"_f16")
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(EXEC), operands = src(1, 1))
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(EXEC), operands = src(1, 1))
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(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0x28+i, 0x28+i, 0xe8+i, 0x08+i, "v_cmp_"+COMPF[i+8]+"_f16")
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(VCC), operands = src(1, 1))
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(VCC), operands = src(1, 1))
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(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0x38+i, 0x38+i, 0xf8+i, 0x88+i, "v_cmpx_"+COMPF[i+8]+"_f16")
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opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(EXEC), operands = src(1, 1))
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(EXEC), operands = src(1, 1))
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|
||||
for i in range(16):
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x00+i, 0x00+i, 0x40+i, 0x40+i, 0x00+i, 0x10+i, "v_cmp_"+COMPF[i]+"_f32")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x10+i, 0x10+i, 0x50+i, 0x50+i, 0x10+i, 0x90+i, "v_cmpx_"+COMPF[i]+"_f32")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, True, False, definitions = dst(EXEC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x20+i, 0x20+i, 0x60+i, 0x60+i, 0x20+i, 0x20+i, "v_cmp_"+COMPF[i]+"_f64")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.ValuDouble, True, False, definitions = dst(VCC), operands = src(2, 2))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.ValuDouble, True, False, definitions = dst(VCC), operands = src(2, 2))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x30+i, 0x30+i, 0x70+i, 0x70+i, 0x30+i, 0xa0+i, "v_cmpx_"+COMPF[i]+"_f64")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.ValuDouble, True, False, definitions = dst(EXEC), operands = src(2, 2))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.ValuDouble, True, False, definitions = dst(EXEC), operands = src(2, 2))
|
||||
# GFX_6_7
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x40+i, 0x40+i, -1, -1, -1, -1, "v_cmps_"+COMPF[i]+"_f32")
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x50+i, 0x50+i, -1, -1, -1, -1, "v_cmpsx_"+COMPF[i]+"_f32")
|
||||
|
|
@ -1014,41 +1014,41 @@ COMPI = ["f", "lt", "eq", "le", "gt", "lg", "ge", "tru"]
|
|||
# GFX_8_9
|
||||
for i in [0,7]: # only 0 and 7
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xa0+i, 0xa0+i, -1, -1, "v_cmp_"+COMPI[i]+"_i16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xb0+i, 0xb0+i, -1, -1, "v_cmpx_"+COMPI[i]+"_i16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xa8+i, 0xa8+i, -1, -1, "v_cmp_"+COMPI[i]+"_u16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xb8+i, 0xb8+i, -1, -1, "v_cmpx_"+COMPI[i]+"_u16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
|
||||
for i in range(1, 7): # [1..6]
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xa0+i, 0xa0+i, 0x88+i, 0x30+i, "v_cmp_"+COMPI[i]+"_i16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xb0+i, 0xb0+i, 0x98+i, 0xb0+i, "v_cmpx_"+COMPI[i]+"_i16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xa8+i, 0xa8+i, 0xa8+i, 0x38+i, "v_cmp_"+COMPI[i]+"_u16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, 0xb8+i, 0xb8+i, 0xb8+i, 0xb8+i, "v_cmpx_"+COMPI[i]+"_u16")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
|
||||
for i in range(8):
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x80+i, 0x80+i, 0xc0+i, 0xc0+i, 0x80+i, 0x40+i, "v_cmp_"+COMPI[i]+"_i32")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0x90+i, 0x90+i, 0xd0+i, 0xd0+i, 0x90+i, 0xc0+i, "v_cmpx_"+COMPI[i]+"_i32")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0xa0+i, 0xa0+i, 0xe0+i, 0xe0+i, 0xa0+i, 0x50+i, "v_cmp_"+COMPI[i]+"_i64")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(VCC), operands = src(2, 2))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(VCC), operands = src(2, 2))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0xb0+i, 0xb0+i, 0xf0+i, 0xf0+i, 0xb0+i, 0xd0+i, "v_cmpx_"+COMPI[i]+"_i64")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(EXEC), operands = src(2, 2))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(EXEC), operands = src(2, 2))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0xc0+i, 0xc0+i, 0xc8+i, 0xc8+i, 0xc0+i, 0x48+i, "v_cmp_"+COMPI[i]+"_u32")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(VCC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0xd0+i, 0xd0+i, 0xd8+i, 0xd8+i, 0xd0+i, 0xc8+i, "v_cmpx_"+COMPI[i]+"_u32")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu32, definitions = dst(EXEC), operands = src(1, 1))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0xe0+i, 0xe0+i, 0xe8+i, 0xe8+i, 0xe0+i, 0x58+i, "v_cmp_"+COMPI[i]+"_u64")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(VCC), operands = src(2, 2))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(VCC), operands = src(2, 2))
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (0xf0+i, 0xf0+i, 0xf8+i, 0xf8+i, 0xf0+i, 0xd8+i, "v_cmpx_"+COMPI[i]+"_u64")
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(EXEC), operands = src(2, 2))
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, InstrClass.Valu64, definitions = dst(EXEC), operands = src(2, 2))
|
||||
|
||||
|
||||
# VOPP instructions: packed 16bit instructions - 2 or 3 inputs and 1 output
|
||||
|
|
@ -1080,22 +1080,22 @@ VOPP = {
|
|||
# note that these are only supported on gfx9+ so we'll need to distinguish between gfx8 and gfx9 here
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, -1, code, code, code, name)
|
||||
for (code, name, modifiers, defs, ops) in VOPP:
|
||||
opcode(name, -1, code, code, code, Format.VOP3P, InstrClass.Valu32, modifiers, modifiers, definitions = defs, operands = ops)
|
||||
opcode("v_dot2_i32_i16", -1, 0x26, 0x14, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot2_u32_u16", -1, 0x27, 0x15, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot4_i32_iu8", -1, -1, -1, 0x16, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot4_i32_i8", -1, 0x28, 0x16, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot4_u32_u8", -1, 0x29, 0x17, 0x17, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot8_i32_iu4", -1, -1, -1, 0x18, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot8_u32_u4", -1, 0x2b, 0x19, 0x19, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot2_f32_f16", -1, 0x23, 0x13, 0x13, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_dot2_f32_bf16", -1, -1, -1, 0x1a, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
opcode("v_wmma_f32_16x16x16_f16", -1, -1, -1, 0x40, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
opcode("v_wmma_f32_16x16x16_bf16", -1, -1, -1, 0x41, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
opcode("v_wmma_f16_16x16x16_f16", -1, -1, -1, 0x42, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
opcode("v_wmma_bf16_16x16x16_bf16", -1, -1, -1, 0x43, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
opcode("v_wmma_i32_16x16x16_iu8", -1, -1, -1, 0x44, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
opcode("v_wmma_i32_16x16x16_iu4", -1, -1, -1, 0x45, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
insn(name, -1, code, code, code, Format.VOP3P, InstrClass.Valu32, modifiers, modifiers, definitions = defs, operands = ops)
|
||||
insn("v_dot2_i32_i16", -1, 0x26, 0x14, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot2_u32_u16", -1, 0x27, 0x15, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot4_i32_iu8", -1, -1, -1, 0x16, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot4_i32_i8", -1, 0x28, 0x16, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot4_u32_u8", -1, 0x29, 0x17, 0x17, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot8_i32_iu4", -1, -1, -1, 0x18, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot8_u32_u4", -1, 0x2b, 0x19, 0x19, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot2_f32_f16", -1, 0x23, 0x13, 0x13, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_dot2_f32_bf16", -1, -1, -1, 0x1a, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn("v_wmma_f32_16x16x16_f16", -1, -1, -1, 0x40, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
insn("v_wmma_f32_16x16x16_bf16", -1, -1, -1, 0x41, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
insn("v_wmma_f16_16x16x16_f16", -1, -1, -1, 0x42, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
insn("v_wmma_bf16_16x16x16_bf16", -1, -1, -1, 0x43, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
insn("v_wmma_i32_16x16x16_iu8", -1, -1, -1, 0x44, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
insn("v_wmma_i32_16x16x16_iu4", -1, -1, -1, 0x45, Format.VOP3P, InstrClass.WMMA, False, False)
|
||||
|
||||
|
||||
# VINTRP (GFX6 - GFX10.3) instructions:
|
||||
|
|
@ -1106,7 +1106,7 @@ VINTRP = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, code, name)
|
||||
for (code, name, defs, ops) in VINTRP:
|
||||
opcode(name, code, code, code, -1, Format.VINTRP, InstrClass.Valu32, definitions = defs, operands = ops)
|
||||
insn(name, code, code, code, -1, Format.VINTRP, InstrClass.Valu32, definitions = defs, operands = ops)
|
||||
|
||||
|
||||
# VINTERP (GFX11+) instructions:
|
||||
|
|
@ -1119,7 +1119,7 @@ VINTERP = {
|
|||
(0x05, "v_interp_p2_rtz_f16_f32_inreg"),
|
||||
}
|
||||
for (code, name) in VINTERP:
|
||||
opcode(name, -1, -1, -1, code, Format.VINTERP_INREG, InstrClass.Valu32, False, True, definitions = dst(1), operands = src(1, 1, 1))
|
||||
insn(name, -1, -1, -1, code, Format.VINTERP_INREG, InstrClass.Valu32, False, True, definitions = dst(1), operands = src(1, 1, 1))
|
||||
|
||||
|
||||
# VOP3 instructions: 3 inputs, 1 output
|
||||
|
|
@ -1272,7 +1272,7 @@ VOP3 = {
|
|||
( -1, -1, -1, -1, -1, 0x25d, "v_cndmask_b16", True, False, dst(1), src(1, 1, VCC)),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, in_mod, out_mod, defs, ops, cls) in default_class(VOP3, InstrClass.Valu32):
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.VOP3, cls, in_mod, out_mod, definitions = defs, operands = ops)
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOP3, cls, in_mod, out_mod, definitions = defs, operands = ops)
|
||||
|
||||
|
||||
VOPD = {
|
||||
|
|
@ -1295,7 +1295,7 @@ VOPD = {
|
|||
(0x12, "v_dual_and_b32"),
|
||||
}
|
||||
for gfx11, name in VOPD:
|
||||
opcode(name, -1, -1, -1, gfx11, format = Format.VOPD, cls = InstrClass.Valu32)
|
||||
insn(name, -1, -1, -1, gfx11, format = Format.VOPD, cls = InstrClass.Valu32)
|
||||
|
||||
|
||||
# DS instructions: 3 inputs (1 addr, 2 data), 1 output
|
||||
|
|
@ -1459,7 +1459,7 @@ DS = {
|
|||
( -1, -1, -1, -1, -1, 0x7b, "ds_sub_gs_reg_rtn"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in DS:
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.DS, InstrClass.DS)
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.DS, InstrClass.DS)
|
||||
|
||||
|
||||
# LDSDIR instructions:
|
||||
|
|
@ -1468,7 +1468,7 @@ LDSDIR = {
|
|||
(0x01, "lds_direct_load"),
|
||||
}
|
||||
for (code, name) in LDSDIR:
|
||||
opcode(name, -1, -1, -1, code, Format.LDSDIR, InstrClass.DS)
|
||||
insn(name, -1, -1, -1, code, Format.LDSDIR, InstrClass.DS)
|
||||
|
||||
# MUBUF instructions:
|
||||
MUBUF = {
|
||||
|
|
@ -1561,7 +1561,7 @@ MUBUF = {
|
|||
( -1, -1, -1, -1, -1, 0x56, "buffer_atomic_add_f32"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in MUBUF:
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.MUBUF, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.MUBUF, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
|
||||
MTBUF = {
|
||||
(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, "tbuffer_load_format_x"),
|
||||
|
|
@ -1582,7 +1582,7 @@ MTBUF = {
|
|||
( -1, -1, 0x0f, 0x0f, 0x0f, 0x0f, "tbuffer_store_format_d16_xyzw"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in MTBUF:
|
||||
opcode(name, gfx7, gfx9, gfx10, gfx11, Format.MTBUF, InstrClass.VMem)
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.MTBUF, InstrClass.VMem)
|
||||
|
||||
|
||||
IMAGE = {
|
||||
|
|
@ -1601,9 +1601,9 @@ IMAGE = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, name)
|
||||
for (code, gfx11, name) in IMAGE:
|
||||
opcode(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
|
||||
opcode("image_msaa_load", -1, -1, 0x80, 0x18, Format.MIMG, InstrClass.VMem) #GFX10.3+
|
||||
insn("image_msaa_load", -1, -1, 0x80, 0x18, Format.MIMG, InstrClass.VMem) #GFX10.3+
|
||||
|
||||
IMAGE_ATOMIC = {
|
||||
(0x0f, 0x0f, 0x10, 0x0a, "image_atomic_swap"),
|
||||
|
|
@ -1627,7 +1627,7 @@ IMAGE_ATOMIC = {
|
|||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (gfx6, gfx7, gfx89, gfx89, ???, gfx11, name)
|
||||
# gfx7 and gfx10 opcodes are the same here
|
||||
for (gfx6, gfx7, gfx89, gfx11, name) in IMAGE_ATOMIC:
|
||||
opcode(name, gfx7, gfx89, gfx7, gfx11, Format.MIMG, InstrClass.VMem, is_atomic = True)
|
||||
insn(name, gfx7, gfx89, gfx7, gfx11, Format.MIMG, InstrClass.VMem, is_atomic = True)
|
||||
|
||||
IMAGE_SAMPLE = {
|
||||
(0x20, 0x1b, "image_sample"),
|
||||
|
|
@ -1673,7 +1673,7 @@ IMAGE_SAMPLE = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, gfx11, name)
|
||||
for (code, gfx11, name) in IMAGE_SAMPLE:
|
||||
opcode(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
|
||||
IMAGE_SAMPLE_G16 = {
|
||||
(0xa2, 0x39, "image_sample_d_g16"),
|
||||
|
|
@ -1688,7 +1688,7 @@ IMAGE_SAMPLE_G16 = {
|
|||
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, -1, -1, code, gfx11, name)
|
||||
for (code, gfx11, name) in IMAGE_SAMPLE_G16:
|
||||
opcode(name, -1, -1, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, -1, -1, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
|
||||
IMAGE_GATHER4 = {
|
||||
(0x40, 0x2f, "image_gather4"),
|
||||
|
|
@ -1721,10 +1721,10 @@ IMAGE_GATHER4 = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, gfx11, name)
|
||||
for (code, gfx11, name) in IMAGE_GATHER4:
|
||||
opcode(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
|
||||
opcode("image_bvh_intersect_ray", -1, -1, 0xe6, 0x19, Format.MIMG, InstrClass.VMem)
|
||||
opcode("image_bvh64_intersect_ray", -1, -1, 0xe7, 0x1a, Format.MIMG, InstrClass.VMem)
|
||||
insn("image_bvh_intersect_ray", -1, -1, 0xe6, 0x19, Format.MIMG, InstrClass.VMem)
|
||||
insn("image_bvh64_intersect_ray", -1, -1, 0xe7, 0x1a, Format.MIMG, InstrClass.VMem)
|
||||
|
||||
FLAT = {
|
||||
#GFX7, GFX89,GFX10,GFX11
|
||||
|
|
@ -1785,7 +1785,7 @@ FLAT = {
|
|||
( -1, -1, -1, 0x56, "flat_atomic_add_f32"),
|
||||
}
|
||||
for (gfx7, gfx8, gfx10, gfx11, name) in FLAT:
|
||||
opcode(name, gfx7, gfx8, gfx10, gfx11, Format.FLAT, InstrClass.VMem, is_atomic = "atomic" in name) #TODO: also LDS?
|
||||
insn(name, gfx7, gfx8, gfx10, gfx11, Format.FLAT, InstrClass.VMem, is_atomic = "atomic" in name) #TODO: also LDS?
|
||||
|
||||
GLOBAL = {
|
||||
#GFX89,GFX10,GFX11
|
||||
|
|
@ -1849,7 +1849,7 @@ GLOBAL = {
|
|||
( -1, -1, 0x56, "global_atomic_add_f32"),
|
||||
}
|
||||
for (gfx8, gfx10, gfx11, name) in GLOBAL:
|
||||
opcode(name, -1, gfx8, gfx10, gfx11, Format.GLOBAL, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
insn(name, -1, gfx8, gfx10, gfx11, Format.GLOBAL, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
|
||||
SCRATCH = {
|
||||
#GFX89,GFX10,GFX11
|
||||
|
|
@ -1877,24 +1877,24 @@ SCRATCH = {
|
|||
(0x25, 0x25, 0x23, "scratch_load_short_d16_hi"),
|
||||
}
|
||||
for (gfx8, gfx10, gfx11, name) in SCRATCH:
|
||||
opcode(name, -1, gfx8, gfx10, gfx11, Format.SCRATCH, InstrClass.VMem)
|
||||
insn(name, -1, gfx8, gfx10, gfx11, Format.SCRATCH, InstrClass.VMem)
|
||||
|
||||
# check for duplicate opcode numbers
|
||||
for ver in ['gfx9', 'gfx10', 'gfx11']:
|
||||
op_to_name = {}
|
||||
for op in opcodes.values():
|
||||
if op.format in [Format.PSEUDO, Format.PSEUDO_BRANCH, Format.PSEUDO_BARRIER, Format.PSEUDO_REDUCTION]:
|
||||
for inst in instructions.values():
|
||||
if inst.format in [Format.PSEUDO, Format.PSEUDO_BRANCH, Format.PSEUDO_BARRIER, Format.PSEUDO_REDUCTION]:
|
||||
continue
|
||||
|
||||
num = getattr(op, 'opcode_' + ver)
|
||||
num = getattr(inst, 'opcode_' + ver)
|
||||
if num == -1:
|
||||
continue
|
||||
|
||||
key = (op.format, num)
|
||||
key = (inst.format, num)
|
||||
|
||||
if key in op_to_name:
|
||||
# exceptions
|
||||
names = set([op_to_name[key], op.name])
|
||||
names = set([op_to_name[key], inst.name])
|
||||
if ver in ['gfx8', 'gfx9', 'gfx11'] and names == set(['v_mul_lo_i32', 'v_mul_lo_u32']):
|
||||
continue
|
||||
# v_mad_legacy_f32 is replaced with v_fma_legacy_f32 on GFX10.3
|
||||
|
|
@ -1904,7 +1904,7 @@ for ver in ['gfx9', 'gfx10', 'gfx11']:
|
|||
if ver == 'gfx10' and names == set(['v_mac_legacy_f32', 'v_fmac_legacy_f32']):
|
||||
continue
|
||||
|
||||
print('%s and %s share the same opcode number (%s)' % (op_to_name[key], op.name, ver))
|
||||
print('%s and %s share the same opcode number (%s)' % (op_to_name[key], inst.name, ver))
|
||||
sys.exit(1)
|
||||
else:
|
||||
op_to_name[key] = op.name
|
||||
op_to_name[key] = inst.name
|
||||
|
|
|
|||
|
|
@ -30,31 +30,31 @@ template = """\
|
|||
namespace aco {
|
||||
|
||||
<%
|
||||
opcode_names = sorted(opcodes.keys())
|
||||
can_use_input_modifiers = "".join([opcodes[name].input_mod for name in reversed(opcode_names)])
|
||||
can_use_output_modifiers = "".join([opcodes[name].output_mod for name in reversed(opcode_names)])
|
||||
is_atomic = "".join([opcodes[name].is_atomic for name in reversed(opcode_names)])
|
||||
opcode_names = sorted(instructions.keys())
|
||||
can_use_input_modifiers = "".join([instructions[name].input_mod for name in reversed(opcode_names)])
|
||||
can_use_output_modifiers = "".join([instructions[name].output_mod for name in reversed(opcode_names)])
|
||||
is_atomic = "".join([instructions[name].is_atomic for name in reversed(opcode_names)])
|
||||
%>
|
||||
|
||||
extern const aco::Info instr_info = {
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].opcode_gfx7},
|
||||
${instructions[name].opcode_gfx7},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].opcode_gfx9},
|
||||
${instructions[name].opcode_gfx9},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].opcode_gfx10},
|
||||
${instructions[name].opcode_gfx10},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].opcode_gfx11},
|
||||
${instructions[name].opcode_gfx11},
|
||||
% endfor
|
||||
},
|
||||
std::bitset<${len(opcode_names)}>("${can_use_input_modifiers}"),
|
||||
|
|
@ -67,27 +67,27 @@ extern const aco::Info instr_info = {
|
|||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
aco::Format::${str(opcodes[name].format.name)},
|
||||
aco::Format::${str(instructions[name].format.name)},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].operand_size},
|
||||
${instructions[name].operand_size},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
instr_class::${opcodes[name].cls.value},
|
||||
instr_class::${instructions[name].cls.value},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${hex(opcodes[name].definitions)},
|
||||
${hex(instructions[name].definitions)},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${hex(opcodes[name].operands)},
|
||||
${hex(instructions[name].operands)},
|
||||
% endfor
|
||||
},
|
||||
};
|
||||
|
|
@ -95,7 +95,7 @@ extern const aco::Info instr_info = {
|
|||
}
|
||||
"""
|
||||
|
||||
from aco_opcodes import opcodes
|
||||
from aco_opcodes import instructions
|
||||
from mako.template import Template
|
||||
|
||||
print(Template(template).render(opcodes=opcodes))
|
||||
print(Template(template).render(instructions=instructions))
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ enum class instr_class : uint8_t {
|
|||
count,
|
||||
};
|
||||
|
||||
<% opcode_names = sorted(opcodes.keys()) %>
|
||||
<% opcode_names = sorted(instructions.keys()) %>
|
||||
|
||||
enum class aco_opcode : uint16_t {
|
||||
% for name in opcode_names:
|
||||
|
|
@ -58,7 +58,7 @@ enum class aco_opcode : uint16_t {
|
|||
}
|
||||
#endif /* _ACO_OPCODES_ */"""
|
||||
|
||||
from aco_opcodes import opcodes, InstrClass, Format
|
||||
from aco_opcodes import instructions, InstrClass, Format
|
||||
from mako.template import Template
|
||||
|
||||
print(Template(template).render(opcodes=opcodes, InstrClass=InstrClass, Format=Format))
|
||||
print(Template(template).render(instructions=instructions, InstrClass=InstrClass, Format=Format))
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue