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intel/brw: Use correct execution pipe for lowering SEL on DF

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This is a float operation, let's keep it on the float pipe.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
This commit is contained in:
Kenneth Graunke 2024-03-21 11:02:41 -07:00 • committed by Marge Bot
parent 26d65e96dd
commit 97c7d5113d
1 changed files with 9 additions and 6 deletions
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15
src/intel/compiler/brw_fs_lower.cpp
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@ -637,17 +637,20 @@ brw_fs_lower_alu_restrictions(fs_visitor &s)
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
const brw::fs_builder ibld(&s, block, inst);
enum brw_reg_type type =
brw_reg_type_from_bit_size(32, inst->dst.type);
if (!inst->is_partial_write())
ibld.emit_undef_for_dst(inst);
set_predicate(inst->predicate,
ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0),
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0),
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0)));
ibld.SEL(subscript(inst->dst, type, 0),
subscript(inst->src[0], type, 0),
subscript(inst->src[1], type, 0)));
set_predicate(inst->predicate,
ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1),
subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1),
subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1)));
ibld.SEL(subscript(inst->dst, type, 1),
subscript(inst->src[0], type, 1),
subscript(inst->src[1], type, 1)));
inst->remove(block);
progress = true;