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aco: use single tuple for all opcode numbers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
This commit is contained in:
Rhys Perry
Marge Bot
parent
5864c22fb7
commit
a806e48982
2 changed files with 83 additions and 65 deletions
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@ -28,6 +28,7 @@ import sys
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import itertools
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import collections
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from enum import Enum, IntEnum, auto
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from collections import namedtuple
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class InstrClass(Enum):
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Valu32 = "valu32"
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@ -224,27 +225,26 @@ class Format(IntEnum):
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return res
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Opcode = namedtuple('Opcode', ['gfx6', 'gfx7', 'gfx8', 'gfx9', 'gfx10', 'gfx11'],
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defaults=[-1, -1, -1, -1, -1, -1])
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class Instruction(object):
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"""Class that represents all the information we have about the opcode
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NOTE: this must be kept in sync with aco_op_info
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"""
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def __init__(self, name, opcode_gfx7, opcode_gfx9, opcode_gfx10, opcode_gfx11, format, input_mod, output_mod, is_atomic, cls, definitions, operands):
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def __init__(self, name, opcode, format, input_mod, output_mod, is_atomic, cls, definitions, operands):
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assert isinstance(name, str)
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assert isinstance(opcode_gfx7, int)
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assert isinstance(opcode_gfx9, int)
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assert isinstance(opcode_gfx10, int)
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assert isinstance(opcode_gfx11, int)
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assert isinstance(opcode, Opcode)
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assert isinstance(format, Format)
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assert isinstance(input_mod, bool)
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assert isinstance(output_mod, bool)
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assert isinstance(definitions, int)
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assert isinstance(operands, int)
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assert opcode.gfx6 == -1 or opcode.gfx7 == -1 or opcode.gfx6 == opcode.gfx7
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assert opcode.gfx8 == -1 or opcode.gfx9 == -1 or opcode.gfx8 == opcode.gfx9
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self.name = name
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self.opcode_gfx7 = opcode_gfx7
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self.opcode_gfx9 = opcode_gfx9
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self.opcode_gfx10 = opcode_gfx10
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self.opcode_gfx11 = opcode_gfx11
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self.op = opcode
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self.input_mod = "1" if input_mod else "0"
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self.output_mod = "1" if output_mod else "0"
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self.is_atomic = "1" if is_atomic else "0"
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@ -294,12 +294,29 @@ def src(op1 = 0, op2 = 0, op3 = 0, op4 = 0):
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def dst(def1 = 0, def2 = 0, def3 = 0, def4 = 0):
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return def1 | (def2 << 8) | (def3 << 16) | (def4 << 24)
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def op(*args, **kwargs):
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enc = [None] * len(Opcode._fields)
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if len(args) > 0:
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assert(len(args) == 1)
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enc[0] = args[0]
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for gen, val in kwargs.items():
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idx = Opcode._fields.index(gen)
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enc[idx] = val
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for i in range(len(enc)):
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if enc[i] == None:
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enc[i] = enc[i - 1] if i > 0 else -1
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return Opcode(*enc)
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# global dictionary of instructions
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instructions = {}
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def insn(name, opcode_gfx7 = -1, opcode_gfx9 = -1, opcode_gfx10 = -1, opcode_gfx11 = -1, format = Format.PSEUDO, cls = InstrClass.Other, input_mod = False, output_mod = False, is_atomic = False, definitions = 0, operands = 0):
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def insn(name, opcode = Opcode(), format = Format.PSEUDO, cls = InstrClass.Other, input_mod = False, output_mod = False, is_atomic = False, definitions = 0, operands = 0):
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assert name not in instructions
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instructions[name] = Instruction(name, opcode_gfx7, opcode_gfx9, opcode_gfx10, opcode_gfx11, format, input_mod, output_mod, is_atomic, cls, definitions, operands)
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instructions[name] = Instruction(name, opcode, format, input_mod, output_mod, is_atomic, cls, definitions, operands)
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def default_class(instructions, cls):
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for i in instructions:
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@ -308,7 +325,7 @@ def default_class(instructions, cls):
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else:
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yield i + (cls,)
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insn("exp", 0, 0, 0, 0, format = Format.EXP, cls = InstrClass.Export)
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insn("exp", op(0), format = Format.EXP, cls = InstrClass.Export)
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insn("p_parallelcopy")
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insn("p_startpgm")
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insn("p_return")
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@ -488,7 +505,7 @@ SOP2 = {
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( -1, -1, -1, -1, -1, -1, "p_resumeaddr_addlo", dst(1, SCC), src(1, 1, 1)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOP2, InstrClass.Salu):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOP2, cls, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.SOP2, cls, definitions = defs, operands = ops)
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# SOPK instructions: 0 input (+ imm), 1 output + optional scc
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@ -524,7 +541,7 @@ SOPK = {
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( -1, -1, -1, -1, 0x1c, 0x17, "s_subvector_loop_end", dst(), src(), InstrClass.Branch),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOPK, InstrClass.Salu):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOPK, cls, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.SOPK, cls, definitions = defs, operands = ops)
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# SOP1 instructions: 1 input, 1 output (+optional SCC)
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@ -606,7 +623,7 @@ SOP1 = {
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( -1, -1, -1, -1, -1, -1, "p_load_symbol", dst(1), src(1)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOP1, InstrClass.Salu):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOP1, cls, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.SOP1, cls, definitions = defs, operands = ops)
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# SOPC instructions: 2 inputs and 0 outputs (+SCC)
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@ -634,7 +651,7 @@ SOPC = {
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( -1, -1, 0x13, 0x13, 0x13, 0x11, "s_cmp_lg_u64", dst(SCC), src(2, 2)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops) in SOPC:
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOPC, InstrClass.Salu, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.SOPC, InstrClass.Salu, definitions = defs, operands = ops)
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# SOPP instructions: 0 inputs (+optional scc/vcc), 0 outputs
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@ -683,7 +700,7 @@ SOPP = {
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( -1, -1, -1, -1, -1, 0x0b, "s_wait_event", dst(), src()),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(SOPP, InstrClass.Salu):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SOPP, cls, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.SOPP, cls, definitions = defs, operands = ops)
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# SMEM instructions: sbase input (2 sgpr), potentially 2 offset inputs, 1 sdata input/output
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@ -778,7 +795,7 @@ SMEM = {
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( -1, -1, -1, 0xac, 0xac, -1, "s_atomic_dec_x2"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in SMEM:
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.SMEM, InstrClass.SMem, is_atomic = "atomic" in name)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.SMEM, InstrClass.SMem, is_atomic = "atomic" in name)
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# VOP2 instructions: 2 inputs, 1 output (+ optional vcc)
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@ -863,7 +880,7 @@ VOP2 = {
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( -1, -1, -1, 0x37, 0x02, 0x02, "v_dot2c_f32_f16", False, False, dst(1), src(1, 1, 1)), #v_dot2acc_f32_f16 in GFX11
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, in_mod, out_mod, defs, ops) in VOP2:
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOP2, InstrClass.Valu32, in_mod, out_mod, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.VOP2, InstrClass.Valu32, in_mod, out_mod, definitions = defs, operands = ops)
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# VOP1 instructions: instructions with 1 input and 1 output
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@ -968,7 +985,7 @@ VOP1 = {
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( -1, -1, -1, -1, -1, 0x1c, "v_mov_b16", True, False, dst(1), src(1)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, in_mod, out_mod, defs, ops, cls) in default_class(VOP1, InstrClass.Valu32):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOP1, cls, in_mod, out_mod, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.VOP1, cls, in_mod, out_mod, definitions = defs, operands = ops)
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# VOPC instructions:
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@ -982,7 +999,7 @@ VOPC_CLASS = {
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(0xb8, 0xb8, 0x13, 0x13, 0xb8, 0xff, "v_cmpx_class_f64", dst(EXEC), src(2, 1), InstrClass.ValuDouble),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, defs, ops, cls) in default_class(VOPC_CLASS, InstrClass.Valu32):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOPC, cls, True, False, definitions = defs, operands = ops)
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insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.VOPC, cls, True, False, definitions = defs, operands = ops)
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VopcDataType = collections.namedtuple('VopcDataTypeInfo',
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['kind', 'size', 'gfx6', 'gfx8', 'gfx10', 'gfx11'])
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@ -1034,7 +1051,8 @@ for comp, dtype, cmps, cmpx in itertools.product(range(16), dtypes, range(1), ra
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elif dtype in [I64, U64]:
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cls = InstrClass.Valu64
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insn(name, gfx6, gfx8, gfx10, gfx11, Format.VOPC, cls, dtype.kind == 'f', False,
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enc = Opcode(gfx6, gfx6, gfx8, gfx8, gfx10, gfx11)
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insn(name, enc, Format.VOPC, cls, dtype.kind == 'f', False,
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definitions = dst(EXEC if cmpx else VCC),
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operands = src(2, 2) if dtype.size == 64 else src(1, 1))
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@ -1068,22 +1086,22 @@ VOPP = {
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# note that these are only supported on gfx9+ so we'll need to distinguish between gfx8 and gfx9 here
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# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, -1, code, code, code, name)
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for (code, name, modifiers, defs, ops) in VOPP:
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insn(name, -1, code, code, code, Format.VOP3P, InstrClass.Valu32, modifiers, modifiers, definitions = defs, operands = ops)
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insn("v_dot2_i32_i16", -1, 0x26, 0x14, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot2_u32_u16", -1, 0x27, 0x15, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot4_i32_iu8", -1, -1, -1, 0x16, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot4_i32_i8", -1, 0x28, 0x16, -1, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot4_u32_u8", -1, 0x29, 0x17, 0x17, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot8_i32_iu4", -1, -1, -1, 0x18, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot8_u32_u4", -1, 0x2b, 0x19, 0x19, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot2_f32_f16", -1, 0x23, 0x13, 0x13, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot2_f32_bf16", -1, -1, -1, 0x1a, Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_wmma_f32_16x16x16_f16", -1, -1, -1, 0x40, Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_f32_16x16x16_bf16", -1, -1, -1, 0x41, Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_f16_16x16x16_f16", -1, -1, -1, 0x42, Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_bf16_16x16x16_bf16", -1, -1, -1, 0x43, Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_i32_16x16x16_iu8", -1, -1, -1, 0x44, Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_i32_16x16x16_iu4", -1, -1, -1, 0x45, Format.VOP3P, InstrClass.WMMA, False, False)
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insn(name, Opcode(-1, -1, -1, code, code, code), Format.VOP3P, InstrClass.Valu32, modifiers, modifiers, definitions = defs, operands = ops)
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insn("v_dot2_i32_i16", Opcode(-1, -1, -1, 0x26, 0x14, -1), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot2_u32_u16", Opcode(-1, -1, -1, 0x27, 0x15, -1), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot4_i32_iu8", Opcode(-1, -1, -1, -1, -1, 0x16), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot4_i32_i8", Opcode(-1, -1, -1, 0x28, 0x16, -1), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot4_u32_u8", Opcode(-1, -1, -1, 0x29, 0x17, 0x17), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot8_i32_iu4", Opcode(-1, -1, -1, -1, -1, 0x18), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot8_u32_u4", Opcode(-1, -1, -1, 0x2b, 0x19, 0x19), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot2_f32_f16", Opcode(-1, -1, -1, 0x23, 0x13, 0x13), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_dot2_f32_bf16", Opcode(-1, -1, -1, -1, -1, 0x1a), Format.VOP3P, InstrClass.Valu32, definitions = dst(1), operands = src(1, 1, 1))
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insn("v_wmma_f32_16x16x16_f16", Opcode(-1, -1, -1, -1, -1, 0x40), Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_f32_16x16x16_bf16", Opcode(-1, -1, -1, -1, -1, 0x41), Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_f16_16x16x16_f16", Opcode(-1, -1, -1, -1, -1, 0x42), Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_bf16_16x16x16_bf16", Opcode(-1, -1, -1, -1, -1, 0x43), Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_i32_16x16x16_iu8", Opcode(-1, -1, -1, -1, -1, 0x44), Format.VOP3P, InstrClass.WMMA, False, False)
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insn("v_wmma_i32_16x16x16_iu4", Opcode(-1, -1, -1, -1, -1, 0x45), Format.VOP3P, InstrClass.WMMA, False, False)
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# VINTRP (GFX6 - GFX10.3) instructions:
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@ -1094,7 +1112,7 @@ VINTRP = {
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}
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# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, code, name)
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for (code, name, defs, ops) in VINTRP:
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insn(name, code, code, code, -1, Format.VINTRP, InstrClass.Valu32, definitions = defs, operands = ops)
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insn(name, Opcode(code, code, code, code, code, -1), Format.VINTRP, InstrClass.Valu32, definitions = defs, operands = ops)
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# VINTERP (GFX11+) instructions:
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@ -1107,7 +1125,7 @@ VINTERP = {
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(0x05, "v_interp_p2_rtz_f16_f32_inreg"),
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}
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for (code, name) in VINTERP:
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insn(name, -1, -1, -1, code, Format.VINTERP_INREG, InstrClass.Valu32, False, True, definitions = dst(1), operands = src(1, 1, 1))
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insn(name, Opcode(-1, -1, -1, -1, -1, code), Format.VINTERP_INREG, InstrClass.Valu32, False, True, definitions = dst(1), operands = src(1, 1, 1))
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# VOP3 instructions: 3 inputs, 1 output
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@ -1260,7 +1278,7 @@ VOP3 = {
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( -1, -1, -1, -1, -1, 0x25d, "v_cndmask_b16", True, False, dst(1), src(1, 1, VCC)),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name, in_mod, out_mod, defs, ops, cls) in default_class(VOP3, InstrClass.Valu32):
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insn(name, gfx7, gfx9, gfx10, gfx11, Format.VOP3, cls, in_mod, out_mod, definitions = defs, operands = ops)
|
||||
insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.VOP3, cls, in_mod, out_mod, definitions = defs, operands = ops)
|
||||
|
||||
|
||||
VOPD = {
|
||||
|
|
@ -1283,7 +1301,7 @@ VOPD = {
|
|||
(0x12, "v_dual_and_b32"),
|
||||
}
|
||||
for gfx11, name in VOPD:
|
||||
insn(name, -1, -1, -1, gfx11, format = Format.VOPD, cls = InstrClass.Valu32)
|
||||
insn(name, Opcode(-1, -1, -1, -1, -1, gfx11), format = Format.VOPD, cls = InstrClass.Valu32)
|
||||
|
||||
|
||||
# DS instructions: 3 inputs (1 addr, 2 data), 1 output
|
||||
|
|
@ -1447,7 +1465,7 @@ DS = {
|
|||
( -1, -1, -1, -1, -1, 0x7b, "ds_sub_gs_reg_rtn"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in DS:
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.DS, InstrClass.DS)
|
||||
insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.DS, InstrClass.DS)
|
||||
|
||||
|
||||
# LDSDIR instructions:
|
||||
|
|
@ -1456,7 +1474,7 @@ LDSDIR = {
|
|||
(0x01, "lds_direct_load"),
|
||||
}
|
||||
for (code, name) in LDSDIR:
|
||||
insn(name, -1, -1, -1, code, Format.LDSDIR, InstrClass.DS)
|
||||
insn(name, Opcode(-1, -1, -1, -1, -1, code), Format.LDSDIR, InstrClass.DS)
|
||||
|
||||
# MUBUF instructions:
|
||||
MUBUF = {
|
||||
|
|
@ -1549,7 +1567,7 @@ MUBUF = {
|
|||
( -1, -1, -1, -1, -1, 0x56, "buffer_atomic_add_f32"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in MUBUF:
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.MUBUF, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.MUBUF, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
|
||||
MTBUF = {
|
||||
(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, "tbuffer_load_format_x"),
|
||||
|
|
@ -1570,7 +1588,7 @@ MTBUF = {
|
|||
( -1, -1, 0x0f, 0x0f, 0x0f, 0x0f, "tbuffer_store_format_d16_xyzw"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) in MTBUF:
|
||||
insn(name, gfx7, gfx9, gfx10, gfx11, Format.MTBUF, InstrClass.VMem)
|
||||
insn(name, Opcode(gfx6, gfx7, gfx8, gfx9, gfx10, gfx11), Format.MTBUF, InstrClass.VMem)
|
||||
|
||||
|
||||
IMAGE = {
|
||||
|
|
@ -1589,9 +1607,9 @@ IMAGE = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, name)
|
||||
for (code, gfx11, name) in IMAGE:
|
||||
insn(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, Opcode(code, code, code, code, code, gfx11), Format.MIMG, InstrClass.VMem)
|
||||
|
||||
insn("image_msaa_load", -1, -1, 0x80, 0x18, Format.MIMG, InstrClass.VMem) #GFX10.3+
|
||||
insn("image_msaa_load", Opcode(-1, -1, -1, -1, 0x80, 0x18), Format.MIMG, InstrClass.VMem) #GFX10.3+
|
||||
|
||||
IMAGE_ATOMIC = {
|
||||
(0x0f, 0x0f, 0x10, 0x0a, "image_atomic_swap"),
|
||||
|
|
@ -1615,7 +1633,7 @@ IMAGE_ATOMIC = {
|
|||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (gfx6, gfx7, gfx89, gfx89, ???, gfx11, name)
|
||||
# gfx7 and gfx10 opcodes are the same here
|
||||
for (gfx6, gfx7, gfx89, gfx11, name) in IMAGE_ATOMIC:
|
||||
insn(name, gfx7, gfx89, gfx7, gfx11, Format.MIMG, InstrClass.VMem, is_atomic = True)
|
||||
insn(name, Opcode(gfx6, gfx7, gfx89, gfx89, gfx7, gfx11), Format.MIMG, InstrClass.VMem, is_atomic = True)
|
||||
|
||||
IMAGE_SAMPLE = {
|
||||
(0x20, 0x1b, "image_sample"),
|
||||
|
|
@ -1661,7 +1679,7 @@ IMAGE_SAMPLE = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, gfx11, name)
|
||||
for (code, gfx11, name) in IMAGE_SAMPLE:
|
||||
insn(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, Opcode(code, code, code, code, code, gfx11), Format.MIMG, InstrClass.VMem)
|
||||
|
||||
IMAGE_SAMPLE_G16 = {
|
||||
(0xa2, 0x39, "image_sample_d_g16"),
|
||||
|
|
@ -1676,7 +1694,7 @@ IMAGE_SAMPLE_G16 = {
|
|||
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (-1, -1, -1, -1, code, gfx11, name)
|
||||
for (code, gfx11, name) in IMAGE_SAMPLE_G16:
|
||||
insn(name, -1, -1, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, Opcode(-1, -1, -1, -1, code, gfx11), Format.MIMG, InstrClass.VMem)
|
||||
|
||||
IMAGE_GATHER4 = {
|
||||
(0x40, 0x2f, "image_gather4"),
|
||||
|
|
@ -1709,10 +1727,10 @@ IMAGE_GATHER4 = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, gfx11, name) = (code, code, code, code, code, gfx11, name)
|
||||
for (code, gfx11, name) in IMAGE_GATHER4:
|
||||
insn(name, code, code, code, gfx11, Format.MIMG, InstrClass.VMem)
|
||||
insn(name, Opcode(code, code, code, code, code, gfx11), Format.MIMG, InstrClass.VMem)
|
||||
|
||||
insn("image_bvh_intersect_ray", -1, -1, 0xe6, 0x19, Format.MIMG, InstrClass.VMem)
|
||||
insn("image_bvh64_intersect_ray", -1, -1, 0xe7, 0x1a, Format.MIMG, InstrClass.VMem)
|
||||
insn("image_bvh_intersect_ray", Opcode(-1, -1, -1, -1, 0xe6, 0x19), Format.MIMG, InstrClass.VMem)
|
||||
insn("image_bvh64_intersect_ray", Opcode(-1, -1, -1, -1, 0xe7, 0x1a), Format.MIMG, InstrClass.VMem)
|
||||
|
||||
FLAT = {
|
||||
#GFX7, GFX89,GFX10,GFX11
|
||||
|
|
@ -1773,7 +1791,7 @@ FLAT = {
|
|||
( -1, -1, -1, 0x56, "flat_atomic_add_f32"),
|
||||
}
|
||||
for (gfx7, gfx8, gfx10, gfx11, name) in FLAT:
|
||||
insn(name, gfx7, gfx8, gfx10, gfx11, Format.FLAT, InstrClass.VMem, is_atomic = "atomic" in name) #TODO: also LDS?
|
||||
insn(name, Opcode(-1, gfx7, gfx8, gfx8, gfx10, gfx11), Format.FLAT, InstrClass.VMem, is_atomic = "atomic" in name) #TODO: also LDS?
|
||||
|
||||
GLOBAL = {
|
||||
#GFX89,GFX10,GFX11
|
||||
|
|
@ -1837,7 +1855,7 @@ GLOBAL = {
|
|||
( -1, -1, 0x56, "global_atomic_add_f32"),
|
||||
}
|
||||
for (gfx8, gfx10, gfx11, name) in GLOBAL:
|
||||
insn(name, -1, gfx8, gfx10, gfx11, Format.GLOBAL, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
insn(name, Opcode(-1, -1, gfx8, gfx8, gfx10, gfx11), Format.GLOBAL, InstrClass.VMem, is_atomic = "atomic" in name)
|
||||
|
||||
SCRATCH = {
|
||||
#GFX89,GFX10,GFX11
|
||||
|
|
@ -1865,20 +1883,20 @@ SCRATCH = {
|
|||
(0x25, 0x25, 0x23, "scratch_load_short_d16_hi"),
|
||||
}
|
||||
for (gfx8, gfx10, gfx11, name) in SCRATCH:
|
||||
insn(name, -1, gfx8, gfx10, gfx11, Format.SCRATCH, InstrClass.VMem)
|
||||
insn(name, Opcode(-1, -1, gfx8, gfx8, gfx10, gfx11), Format.SCRATCH, InstrClass.VMem)
|
||||
|
||||
# check for duplicate opcode numbers
|
||||
for ver in ['gfx9', 'gfx10', 'gfx11']:
|
||||
for ver in Opcode._fields:
|
||||
op_to_name = {}
|
||||
for inst in instructions.values():
|
||||
if inst.format in [Format.PSEUDO, Format.PSEUDO_BRANCH, Format.PSEUDO_BARRIER, Format.PSEUDO_REDUCTION]:
|
||||
continue
|
||||
|
||||
num = getattr(inst, 'opcode_' + ver)
|
||||
if num == -1:
|
||||
opcode = getattr(inst.op, ver)
|
||||
if opcode == -1:
|
||||
continue
|
||||
|
||||
key = (inst.format, num)
|
||||
key = (inst.format, opcode)
|
||||
|
||||
if key in op_to_name:
|
||||
# exceptions
|
||||
|
|
|
|||
|
|
@ -39,22 +39,22 @@ is_atomic = "".join([instructions[name].is_atomic for name in reversed(opcode_na
|
|||
extern const aco::Info instr_info = {
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${instructions[name].opcode_gfx7},
|
||||
${instructions[name].op.gfx7},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${instructions[name].opcode_gfx9},
|
||||
${instructions[name].op.gfx9},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${instructions[name].opcode_gfx10},
|
||||
${instructions[name].op.gfx10},
|
||||
% endfor
|
||||
},
|
||||
{
|
||||
% for name in opcode_names:
|
||||
${instructions[name].opcode_gfx11},
|
||||
${instructions[name].op.gfx11},
|
||||
% endfor
|
||||
},
|
||||
std::bitset<${len(opcode_names)}>("${can_use_input_modifiers}"),
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue