Commit graph

9522 commits

Author SHA1 Message Date
Samuel Pitoiset
f1d103f7de radv: capture shader executable info at shader creation time
This doesn't need to be delayed and it will allow us to support
caching with eg. RADV_DEBUG=hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32246>
2024-11-27 08:04:59 +00:00
Samuel Pitoiset
acc84133f1 radv: only pass relevant stages when emitting DGC push constants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32346>
2024-11-27 07:35:40 +00:00
Marek Olšák
a3516dafc9 util,amd: add inlinable versions of drmIoctl/drmCommandWrite*
The reason for this is to inline those calls in drivers.
They are very trivial, so why not.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32067>
2024-11-26 00:16:02 -05:00
Marek Olšák
049641ca54 amd: import libdrm_amdgpu ioctl wrappers
This imports 35 libdrm_amdgpu functions into Mesa.

The following 15 functions are still in use:
   amdgpu_bo_alloc
   amdgpu_bo_cpu_map
   amdgpu_bo_cpu_unmap
   amdgpu_bo_export
   amdgpu_bo_free
   amdgpu_bo_import
   amdgpu_create_bo_from_user_mem
   amdgpu_device_deinitialize
   amdgpu_device_get_fd
   amdgpu_device_initialize
   amdgpu_get_marketing_name
   amdgpu_query_sw_info
   amdgpu_va_get_start_addr
   amdgpu_va_range_alloc
   amdgpu_va_range_free

We can't import them because they make sure that we only use 1 VMID
per process shared by all APIs. (except the marketing name)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32067>
2024-11-25 21:03:41 -05:00
Hans-Kristian Arntzen
fc9ae4b974 radv: Fix missing gang barriers for task shaders.
It's also possible to use ALL_GRAPHICS and PRE_RASTERIZATION as
alternatives.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32323>
2024-11-25 12:37:47 +00:00
Samuel Pitoiset
ba77b2d65d radv: fix printing with RADV_DEBUG=psocachestats
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32254>
2024-11-25 07:36:49 +00:00
Samuel Pitoiset
6c967c9bbe radv: fix dumping the trap handler shader disassembly
This has been broken in the recent RADV_DEBUG=shaders refactoring.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32254>
2024-11-25 07:36:49 +00:00
Samuel Pitoiset
5c3a757ba6 radv: add a pipeline helper to skip shaders cache
It's common for the three type of pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32254>
2024-11-25 07:36:48 +00:00
Samuel Pitoiset
3f646d43dd radv: fix dumping debug/perftest options when there are holes
Also fix the wrong assertion.

Fixes: 8c1e2ac03b ("radv: Refactor RADV_DEBUG=shaders to be a combination of other options.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32276>
2024-11-25 07:01:06 +00:00
Timur Kristóf
45c523104a ac/nir/ngg: Implement optional primitive compaction.
It's an experimental feature that we may enable later.
Instead of exporting NULL primitives, perform a compaction
on primitives after culling.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32290>
2024-11-25 01:56:20 +01:00
Timur Kristóf
b9d2b5e100 radv: Don't flush at the end of each command buffer on GFX6.
It should be enough to do this at the end of each submit instead.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31695>
2024-11-21 23:23:09 +00:00
Timur Kristóf
030a7510ce radv: Add a flush postamble on GFX6.
Create a CS which contains just a cache flush,
that can be used as a postamble in command submissions.

According to RadeonSI code, the kernel flushes L2
before shaders are finished on GFX6.

Previously, RADV always added a flush at the end of
each command buffer. The flush postamble should be
a less wasteful alternative to that.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31695>
2024-11-21 23:23:09 +00:00
Samuel Pitoiset
aca20fd2e1 radv: mark VERDE (GFX6) as Vulkan 1.3 conformant
https://www.khronos.org/conformance/adopters/conformant-products#submission_820

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32255>
2024-11-20 19:26:20 +00:00
Samuel Pitoiset
08c9dca8db radv: fix skipping on-disk shaders cache when not useful
This was just broken because individual shaders were still stored
on-disk in many situations:
- for shader object, all compute/graphics shaders were stored
- for fast-GPL, graphics shaders were stored
- for pipeline binaries, when the create flag was used
- for rt capture/replay and ray history

This should stop storing unused binaries on-disk and save space.

Found this by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32227>
2024-11-20 10:01:26 +00:00
Samuel Pitoiset
92446a2dcc radv: remove VK_VALVE_descriptor_set_host_mapping
This extension was only enabled for vkd3d-proton and it's obsolete
since VK_EXT_descriptor_buffer, which landed in September 2022.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32218>
2024-11-20 08:56:41 +00:00
Samuel Pitoiset
2abbd361e2 radv,aco: dump LDS from the trap handler
Can be useful for debugging.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32182>
2024-11-20 07:35:47 +00:00
Marek Olšák
25d4943481 nir: make use_interpolated_input_intrinsics a nir_lower_io parameter
This will need to be set to true when the GLSL linker lowers IO, which
can later be unlowered by st/mesa, and then drivers can lower it again
without load_interpolated_input. Therefore, it can't be a global
immutable option.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32229>
2024-11-20 02:45:37 +00:00
Timur Kristóf
cf36fc134e radv: Set dump flags in a smarter way by default.
If shader stages are specified but compilation stages aren't,
dump NIR, backend IR and disassembly.

If compilation stages are specified but shader stages aren't,
dump all shader stages.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:45 +01:00
Timur Kristóf
14ea24ab6f radv: Also allow filtering SPIR-V dump per stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:43 +01:00
Timur Kristóf
e6eaf7b950 radv: Slightly reword preoptir debug flag.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:42 +01:00
Timur Kristóf
8c1e2ac03b radv: Refactor RADV_DEBUG=shaders to be a combination of other options.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:40 +01:00
Timur Kristóf
6d5caabdd7 radv: Separate option to dump backend IR.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:38 +01:00
Timur Kristóf
649da9e744 radv: Separate option to print shader disassembly.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:35 +01:00
Timur Kristóf
3f92c0bbe9 radv: Separate option to dump NIR.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:33 +01:00
Timur Kristóf
d94e65574f aco: Separate options for printing IR and recording disassembly.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:28 +01:00
Timur Kristóf
ab89fdc3d4 radv: Add ability to dump shaders based on stage.
The new debug flags can make the output less overwhelming
and only dump what we want to see.

The old RADV_DEBUG=shaders will still print all stages.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:15:23 +01:00
Timur Kristóf
57161f516e radv: Mark GS copy shaders as internal.
Instead of passing the meta_shader arg.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>
2024-11-19 16:14:45 +01:00
Samuel Pitoiset
2f13723c0a radv: add a new drirc option to disable DCC for mips and enable it for RDR2
The game aliases two images. It binds a memory object to two different
images, the first one being an image with 4 mips and the second with
only one mip but the bind offset is incorrect. It's like it queried
the first image size with different usage flags, so that DCC was
disabled.

Force disabling DCC for mips fixes the incorrect rendering and doesn't
hurt performance.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10200
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32190>
2024-11-19 07:39:13 +00:00
Samuel Pitoiset
2e51d0c724 radv: add a helper to destroy a logical device
It's less error prone than duplicating every cleanups with a bunch of
gotos.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32112>
2024-11-19 07:02:52 +00:00
Samuel Pitoiset
2181ddf383 radv: destroy meta resources properly when creating the device failed
Better to call radv_device_finish_meta().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32112>
2024-11-19 07:02:52 +00:00
Marek Olšák
a7ba36f589 ac/nir: get pass_tessfactors_by_reg from nir_gather_tcs_info
If nir_tcs_info::all_invocations_define_tess_levels is true, the pass
doesn't have to insert a barrier and use output loads to get tess level
output values. It can just use the SSA defs that are being stored (or phis
thereof) to get the tess level output values.

The remaining tcs_info fields will be used by the HS shader message.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32171>
2024-11-16 21:58:29 -05:00
Marek Olšák
b258a9aa4e aco: remove unused TCS fields from aco_shader_info
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32171>
2024-11-16 21:58:26 -05:00
Samuel Pitoiset
d2960a8430 radv: consider VK_PIPELINE_STAGE_2_NONE like BOTTOM_OF_PIPE
VK_PIPELINE_STAGE_2_NONE from sync2 is similar to BOTTOM_OF_PIPE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32115>
2024-11-15 08:22:23 +00:00
Samuel Pitoiset
c08d2c40ed radv: fix ignoring src stage mask when dst stage mask is BOTTOM_OF_PIPE
Otherwise the driver doesn't synchronize if there are image layout
transitions.

This fixes rendering issues with displayable DCC (usually black squares
in the bottom of screen). This mostly happens when an application
uses a lower resolution than the screen supports and fshack
(wine/proton) which upscales images uses COMPUTE_SHADER->BOTTOM_OF_PIPE
for the barrier after a dispatch.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11547
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11600
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11789
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8705
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9890
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32115>
2024-11-15 08:22:23 +00:00
Samuel Pitoiset
45c0ef3bb4 radv: dump SPIR-V and NIR for the faulty shader detected with the trap
More logs is always better for debugging.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32116>
2024-11-14 15:57:07 +00:00
Samuel Pitoiset
9149488a9d radv: mark live invocations when dumping VGPRS with the trap handler
Similar to UMR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32116>
2024-11-14 15:57:07 +00:00
David Rosca
dcfc956521 radv/video: Override pic_init_qp_minus26 in PPS
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
2024-11-14 07:52:56 +00:00
David Rosca
d166bb5dd1 radv/video: Use 64x16 alignment for HEVC encode
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
2024-11-14 07:52:56 +00:00
David Rosca
d1c1a33b35 radv/video: Avoid selecting rc layer over maximum
Vulkan spec doesn't say if this is allowed or not, but trying
to do this will hang.

Fixes: 4a19047d32 ("radv/video: Select temporal layer when encoding each frame")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
2024-11-14 07:52:56 +00:00
David Rosca
e941acfb9d radv/video: Report correct encodeInputPictureGranularity
Only aligned size can be encoded.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
2024-11-14 07:52:56 +00:00
David Rosca
e4ec135d8b radv/video: Fix HEVC slice control
This needs to use aligned size, otherwise it will output two
slices when the size is not 64 aligned.

Fixes: 967e4e09de ("radv/video: add h265 encode support")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
2024-11-14 07:52:56 +00:00
David Rosca
6a121f1507 radv/video: Fix H264 slice control
This needs to use aligned size, otherwise it will output two
slices when the size is not 16 aligned.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31418>
2024-11-14 07:52:56 +00:00
Samuel Pitoiset
b4b5f9eeb0 radv,aco: dump VGPRS from the trap handler shader
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32090>
2024-11-13 15:27:54 +00:00
Rhys Perry
7d4cc04156 radv,ac/nir: split global access using nir_lower_mem_access_bit_sizes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
2024-11-13 12:59:26 +00:00
Rhys Perry
8fdc5d7f9f radv,ac/nir: lower sub-dword loads using nir_lower_mem_access_bit_sizes
fossil-db (navi21):
Totals from 427 (0.54% of 79395) affected shaders:
Instrs: 2939637 -> 2937224 (-0.08%); split: -0.08%, +0.00%
CodeSize: 15982272 -> 15969880 (-0.08%); split: -0.08%, +0.00%
Latency: 21128645 -> 21125738 (-0.01%); split: -0.04%, +0.03%
InvThroughput: 5626811 -> 5626220 (-0.01%); split: -0.03%, +0.02%
SClause: 65771 -> 65731 (-0.06%); split: -0.07%, +0.00%
Copies: 243247 -> 242917 (-0.14%); split: -0.14%, +0.01%
Branches: 100089 -> 100085 (-0.00%)
PreSGPRs: 17879 -> 18118 (+1.34%)
VALU: 1899641 -> 1899278 (-0.02%)
SALU: 468508 -> 466469 (-0.44%)
SMEM: 84305 -> 84291 (-0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
2024-11-13 12:59:26 +00:00
Samuel Pitoiset
44fa24580f radv: optimize the pipe misaligned L2 cache invalidation on GFX11
When using the subresource range, it's possible to reduce the number
of L2 cache invalidations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
2024-11-12 17:27:39 +00:00
Samuel Pitoiset
7a3a65c0c4 radv: pass the image subresource range to radv_{src,dst}_access_flush()
This will allow us to optimize the pipe misaligned special case for
GFX11 because only the first mip in the mip-tail needs the L2 cache
invalidation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
2024-11-12 17:27:39 +00:00
Samuel Pitoiset
f7a39fac10 radv: use vk_image_view_subresource_range() when possible
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
2024-11-12 17:27:39 +00:00
Samuel Pitoiset
7a8b725d03 radv: determine the first mip that is pipe misaligned on GFX10+
This will allow us to optimize the GFX11 case where not all mips are
affected by the L2 invalidation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
2024-11-12 17:27:39 +00:00
Samuel Pitoiset
c5d5f2fbef radv: move the GFX11 special case for mips to radv_image_is_pipe_misaligned()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31921>
2024-11-12 17:27:39 +00:00