radv: Add ability to dump shaders based on stage.

The new debug flags can make the output less overwhelming
and only dump what we want to see.

The old RADV_DEBUG=shaders will still print all stages.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32079>

docs/envvars.rst

@@ -1416,6 +1416,22 @@ RADV driver environment variables
       synchronize shaders after all draws/dispatches
    ``zerovram``
       initialize all memory allocated in VRAM as zero
+   ``vs``
+      Dump vertex shaders.
+   ``tcs``
+      Dump tessellation control shaders.
+   ``tes``
+      Dump tessellation evaluation shaders.
+   ``gs``
+      Dump geometry shaders.
+   ``ps``
+      Dump fragment shaders.
+   ``task``
+      Dump task shaders.
+   ``mesh``
+      Dump mesh shaders.
+   ``cs``
+      Dump compute (and ray tracing) shaders.
 
 .. envvar:: RADV_FORCE_FAMILY
 

src/amd/vulkan/radv_debug.h

@@ -61,6 +61,14 @@ enum {
    RADV_DEBUG_PSO_CACHE_STATS = 1ull << 45,
    RADV_DEBUG_NIR_DEBUG_INFO = 1ull << 46,
    RADV_DEBUG_DUMP_TRAP_HANDLER = 1ull << 47,
+   RADV_DEBUG_DUMP_VS = 1ull << 48,
+   RADV_DEBUG_DUMP_TCS = 1ull << 49,
+   RADV_DEBUG_DUMP_TES = 1ull << 50,
+   RADV_DEBUG_DUMP_GS = 1ull << 51,
+   RADV_DEBUG_DUMP_PS = 1ull << 52,
+   RADV_DEBUG_DUMP_TASK = 1ull << 53,
+   RADV_DEBUG_DUMP_MESH = 1ull << 54,
+   RADV_DEBUG_DUMP_CS = 1ull << 55,
 };
 
 enum {

src/amd/vulkan/radv_instance.c

@@ -74,6 +74,14 @@ static const struct debug_control radv_debug_options[] = {{"nofastclears", RADV_
                                                           {"psocachestats", RADV_DEBUG_PSO_CACHE_STATS},
                                                           {"nirdebuginfo", RADV_DEBUG_NIR_DEBUG_INFO},
                                                           {"dump_trap_handler", RADV_DEBUG_DUMP_TRAP_HANDLER},
+                                                          {"vs", RADV_DEBUG_DUMP_VS},
+                                                          {"tcs", RADV_DEBUG_DUMP_TCS},
+                                                          {"tes", RADV_DEBUG_DUMP_TES},
+                                                          {"gs", RADV_DEBUG_DUMP_GS},
+                                                          {"ps", RADV_DEBUG_DUMP_PS},
+                                                          {"task", RADV_DEBUG_DUMP_TASK},
+                                                          {"mesh", RADV_DEBUG_DUMP_MESH},
+                                                          {"cs", RADV_DEBUG_DUMP_CS},
                                                           {NULL, 0}};
 
 const char *

src/amd/vulkan/radv_pipeline_graphics.c

@@ -2336,7 +2336,9 @@ radv_graphics_shaders_nir_to_asm(struct radv_device *device, struct vk_pipeline_
 
       int64_t stage_start = os_time_get_nano();
 
-      bool dump_shader = radv_can_dump_shader(device, nir_shaders[0]);
+      bool dump_shader = false;
+      for (unsigned i = 0; i < shader_count; ++i)
+         dump_shader |= radv_can_dump_shader(device, nir_shaders[i]);
 
       if (dump_shader) {
          simple_mtx_lock(&instance->shader_dump_mtx);

src/amd/vulkan/radv_shader.c

@@ -95,19 +95,43 @@ is_meta_shader(nir_shader *nir)
    return nir && nir->info.internal;
 }
 
+static uint64_t
+radv_dump_flag_for_stage(const gl_shader_stage stage)
+{
+   switch (stage) {
+   case MESA_SHADER_VERTEX:
+      return RADV_DEBUG_DUMP_VS;
+   case MESA_SHADER_TESS_CTRL:
+      return RADV_DEBUG_DUMP_TCS;
+   case MESA_SHADER_TESS_EVAL:
+      return RADV_DEBUG_DUMP_TES;
+   case MESA_SHADER_GEOMETRY:
+      return RADV_DEBUG_DUMP_GS;
+   case MESA_SHADER_FRAGMENT:
+      return RADV_DEBUG_DUMP_PS;
+   case MESA_SHADER_TASK:
+      return RADV_DEBUG_DUMP_TASK;
+   case MESA_SHADER_MESH:
+      return RADV_DEBUG_DUMP_MESH;
+   default:
+      return RADV_DEBUG_DUMP_CS;
+   }
+}
+
 bool
 radv_can_dump_shader(struct radv_device *device, nir_shader *nir)
 {
    const struct radv_physical_device *pdev = radv_device_physical(device);
    const struct radv_instance *instance = radv_physical_device_instance(pdev);
 
-   if (!(instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
-      return false;
+   if (is_meta_shader(nir))
+      return instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS;
 
-   if (is_meta_shader(nir) && !(instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS))
-      return false;
+   uint64_t flags = RADV_DEBUG_DUMP_SHADERS;
+   if (nir)
+      flags |= radv_dump_flag_for_stage(nir->info.stage);
 
-   return true;
+   return instance->debug_flags & flags;
 }
 
 bool
@@ -3093,9 +3117,13 @@ radv_shader_nir_to_asm(struct radv_device *device, struct radv_shader_stage *pl_
    gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
    struct radv_shader_info *info = &pl_stage->info;
 
+   bool dump_shader = false;
+   for (unsigned i = 0; i < shader_count; ++i)
+      dump_shader |= radv_can_dump_shader(device, shaders[i]);
+
    struct radv_nir_compiler_options options = {0};
    radv_fill_nir_compiler_options(&options, device, gfx_state, radv_should_use_wgp_mode(device, stage, info),
-                                  radv_can_dump_shader(device, shaders[0]), keep_shader_info, keep_statistic_info);
+                                  dump_shader, keep_shader_info, keep_statistic_info);
 
    struct radv_shader_binary *binary =
       shader_compile(device, shaders, shader_count, stage, info, &pl_stage->args, &pl_stage->key, &options);