Commit graph

41930 commits

Author SHA1 Message Date
Marek Olšák
b94c277fd1 radeonsi: enable full out-of-order drawing when allow_draw_out_of_order is set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
2020-03-26 03:08:34 -04:00
Marek Olšák
8c053e5fad mesa: allow out-of-order drawing to optimize immediate mode if it's safe
This increases performance by 11-13% in Viewperf11/Catia - first scene.

Set allow_draw_out_of_order=true to enable this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
2020-03-26 03:08:34 -04:00
Kristian H. Kristensen
d269fb33b0 radeonsi: Stop exposing PIPE_SHADER_CAP_FP16
Not fully supported.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4321>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4321>
2020-03-25 22:43:41 +00:00
Christian Gmeiner
8cdace95ac freedreno: ssbo: mark resource read or written depending on usage
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Christian Gmeiner
061b262a0c freedreno: ssbo: keep track if a buffer gets written
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Christian Gmeiner
0ed053f03d freedreno: simplify fd_set_shader_buffers(..)
Clear the modified bits for enabled_mask and then iterate over the
whole range and set the specific bit where there is a buffer.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Christian Gmeiner
3340cbd398 freedreno: calculate modified bit mask only once
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Roland Scheidegger
3cbcb1b73e gallium/util: Add back (and rename) util_float_to_half implementation
This implementation was removed by 8b8af6d3 ("gallium/util: Switch
util_float_to_half to _mesa_float_to_half()'s impl.")
It was not actually broken, but _mesa_float_to_half() implements
round-to-nearest-even, whereas util_float_to_half() implemented
round-to-zero. So rename it appropriately.
GL actually never cares about rounding (except a broken piglit test),
however d3d10 very much does and requires RTZ for float to half
conversion. Moreover, apparently at least radeon gpus actually always
do RTZ when doing RT writes (and I'd suspect for shader image writes
as well). Hence it seems appropriate to hook up this rtz function to
the format instead. This will cause llvmpipe and softpipe to use rtz
rounding for clears with half float formats, and softpipe would use rtz
behavior for rt writes as well (llvmpipe has that hardcoded), not sure
if "real" hw drivers hit this function for much.
(For shader opcodes would still need to figure out what rounding to use
appropriately, but this is a question for another day.)
Note should probably unify with _mesa_float_to_float16_rtz. Unclear at
this point which one is better, so just restore previous function here.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4312>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4312>
2020-03-25 19:16:13 +00:00
Marek Vasut
9e78f17b74 etnaviv: Emit PE.ALPHA_COLOR_EXT* on GPUs with half-float support
At least GC880 (iMX6S), GC2000 (iMX6Q) blobs do not emit the
PE.ALPHA_COLOR_EXT0 and PE.ALPHA_COLOR_EXT1 into the command
stream. The GCnano (STM32MP1) is not affected by this change
either. This is because neither of these GPUs support the
half-float feature.

Emit PE.ALPHA_COLOR_EXT* in etnaviv only if half-float support
is present in the GPU. This fixes all of the currently failing
dEQPs in this group:
  dEQP-GLES2.functional.fragment_ops.blend.*

Fixes: 76adf041f2 ("etnaviv: fix blend color on newer GPUs")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4277>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4277>
2020-03-25 19:21:05 +01:00
Roland Scheidegger
4897e70ccd gallivm: disable rgtc/latc SNORM accellerated fetches
Unfortunately this appears to be bugged (it seems the piglit tests aren't
quite exhaustive enough). I'm almost certain it's the lerp
(lp_build_lerpdxta()) which doesn't handle signed numbers correctly, let's
disable for now.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4311>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4311>
2020-03-25 17:56:11 +00:00
Erik Faye-Lund
8c30b9d987 rbug: do not return void-value
Returning a void-value is nonsensical, and in this case it seems like a
mistake.

This eliminates a warning when building on MSVC.

Fixes: fb04e5da97 ("gallium: add pipe_screen::finalize_nir")
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
2020-03-25 14:19:37 +00:00
Erik Faye-Lund
411d7429c9 rbug: clean up cast-warnings
Similarly to the previous cast; on 64-bit Windows, unsigned long is
32-bit, and casting a pointer to a non-matchin bit-width integer produce
warnings. So let's use uintpre_t for this purpose instead.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
2020-03-25 14:19:37 +00:00
Erik Faye-Lund
079cb4949d pipebuffer: clean up cast-warnings
This code produces warnings, so let's fix that. The problem is that
casting a pointer to an integer of non-pointer-size triggers warnings on
MSVC, and on 64-bit Windows unsigned long is 32-bit large.

So let's instead use uintptr_t, which is exactly for these kinds of
things.

While we're at it, let's make the resulting index a plain "unsigned",
which is the type this originated from before we started with this
cast-dance.

Fixes: 1a66ead1c7 ("pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flags")
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
2020-03-25 14:19:37 +00:00
Hyunjun Ko
75674ed4d4 freedreno: Enable mediump lowering
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Jonathan Marek
07a8100aed freedreno/registers: more GRAS_CL_CNTL bits, Z_CLAMP
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
2020-03-24 13:01:44 +00:00
Pierre-Eric Pelloux-Prayer
bd6234f24b radeonsi: clarify the conditions when FLUSH_AND_INV_DB is needed
FLUSH_AND_INV_DB should be done when we're changing surface state
registers of a bound depth target.

When depth_clear_value changes, si_state will modify
S_028038_ZRANGE_PRECISION so we need to flush the DB caches.

Verified with the captures from bugs cited below.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1283
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1330
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4263>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4263>
2020-03-24 08:05:12 +01:00
Roman Stratiienko
4ed12efb58 lima: Add missing source file to Android.mk
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4283>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4283>
2020-03-23 19:26:29 +00:00
Sagar Ghuge
c40acdef52 iris: Set patch count threshold in 3DSTATE_HS
Lets specifiy maximum number of patches that will be accumulated before
a thread is dispatched.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
2020-03-23 17:57:57 +00:00
Roman Stratiienko
2a70a1d69d panfrost: Align Android makefiles with recent changes
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
2020-03-23 14:03:22 +00:00
Jan Zielinski
8b3b07afc0 gallium/gallivm: Remove workaround disabling AVX code for newer CPUs
The change enables using full 256-bit AVX and AVX2 instructions
on newer platforms.

Reviewed-by: Alok Hota <alok.hota@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
2020-03-23 09:20:51 +00:00
Dave Airlie
9e3efa4294 gallivm: add support for rgtc/latc fetches.
Annoyingly heaven uses rgtc2 snorm but this at least avoids
the function call overheads to the util fetch functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
2020-03-23 11:02:03 +10:00
Dave Airlie
b3894e52c2 gallivm/s3tc: split out dxt5 alpha code
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
2020-03-23 11:02:00 +10:00
Jonathan Marek
f8bbf44ca4 etnaviv: nir: add compile_check_limits
To match TGSI compiler behaviour in glmark terrain scene for example.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
2020-03-22 00:29:36 +00:00
Marek Olšák
5cc3ab0ba0 vbo,gallium: make glBegin/End buffer size configurable by drivers
The default is 512 KB, but radeonsi wants 4 MB.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
2020-03-21 03:39:51 +00:00
Mark Menzynski
866a8da2a4 tgsi/util: Change boolean for bool
I was getting errors with "boolean" when compiling. This patch changes
boolean to bool from <stdbool.h>.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
2020-03-20 17:25:25 +00:00
Vasily Khoruzhick
1b49534df2 lima: add support for R and RG formats
Unfortunately these are not supported natively for sampling
so we have to lower them.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
2020-03-20 17:00:10 +00:00
Vasily Khoruzhick
e763c6778c lima: split pixel and texel format tables
This is preparation for the next commit where we may need different
swap_r_b flags for pixel and texel formats.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
2020-03-20 17:00:10 +00:00
Erik Faye-Lund
d4b0e28f62 zink/spirv: do not use bitwise operations on booleans
According to the SPIR-V specification, these operations require
integer-types. When bit_size is 1, we use booleans, which makes us emit
illegal code.

So let's fix the emitting to check if the first source is one bit wide.

For inot we can take a short-cut, and check the destination instead.
This doesn't work for ieq and ine, so let's not bother to do this
BINOP_LOG.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
2020-03-20 16:37:30 +00:00
Marek Olšák
7a59d6eaa2 winsys/radeon: change to 3-space indentation
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
2020-03-19 20:33:01 -04:00
Eric Anholt
5b57aa79e2 freedreno: Switch to exposing only half-integer pixel centers.
This is what the HW provides us.  If we need integer pixel centers, we
want the state tracker to do the lowering pass so that it gets to optimize
on the subtract.  This is also the shader instructions that the blob is
doing on GLES, and is what Vulkan wants too, as was noted in MR !4172.

shader-db on a630:
total instructions in shared programs: 186689 -> 186168 (-0.28%)
total nops in shared programs: 66253 -> 66139 (-0.17%)
total non-nops in shared programs: 120436 -> 120029 (-0.34%)
total dwords in shared programs: 292192 -> 291168 (-0.35%)
total last-baryf in shared programs: 4810 -> 4734 (-1.58%)
total full in shared programs: 10176 -> 10195 (0.19%)
total constlen in shared programs: 54589 -> 54575 (-0.03%)
total sstall in shared programs: 24582 -> 24802 (0.89%)
total (ss) in shared programs: 3921 -> 3925 (0.10%)
total (sy) in shared programs: 1934 -> 1923 (-0.57%)

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4223>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4223>
2020-03-19 21:35:49 +00:00
John Stultz
5c8ba96a54 r600: Fix build error in sfn_nir_lower_fs_out_to_vector.cpp
In trying a full build under AOSP, I ran into the following error:

In file included from external/mesa3d/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp:33:
external/libcxx/include/set:942:26: error: the specified comparator type does not provide a const call operator [-Werror,-Wuser-defined-warnings]
    static_assert(sizeof(__diagnose_non_const_comparator<_Key, _Compare>()), "");
                         ^
external/mesa3d/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp:78:34: note: in instantiation of template class 'std::__1::multiset<nir_intrinsic_ins
tr *, r600::nir_intrinsic_instr_less, std::__1::allocator<nir_intrinsic_instr *> >' requested here
   using InstrSubSet = std::pair<InstrSet::iterator, InstrSet::iterator>;
                                 ^
external/libcxx/include/__tree:967:5: note: from 'diagnose_if' attribute on '__diagnose_non_const_comparator<nir_intrinsic_instr *, r600::nir_intrinsic_instr_less>':
    _LIBCPP_DIAGNOSE_WARNING(!std::__invokable<_Compare const&, _Tp const&, _Tp const&>::value,
    ^                        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
external/libcxx/include/__config:1244:21: note: expanded from macro '_LIBCPP_DIAGNOSE_WARNING'
     __attribute__((diagnose_if(__VA_ARGS__, "warning")))
                    ^           ~~~~~~~~~~~
1 error generated.

Which is pretty opaque to me, but searching the web suggested
adding a cost, which seems to resovle it.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
John Stultz
0df48e5d1f vc4_bufmgr: Remove duplicative VC definition
This is already defined in
  src/broadcom/cle/v3d_packet_helpers.h:42:9

And was causing build issues in AOSP when building with mmma

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
John Stultz
e3bbe1fa65 etnaviv: Avoid shift overflow
Building with AOSP I'm seeing:

external/mesa3d/src/gallium/drivers/etnaviv/etnaviv_screen.c:245:31: error: signed shift result (0x100000000) requires 34 bits to represent, but 'int' only has 32 bits [-Werror,-Wshift-overflow]
         system_memory = 4096 << 20;

system_memory is a uint_64t, so this patch addresses the issue
by casting 4096 to a unint_64t before the shift is done.

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
John Stultz
511c6408f4 Android.mk: Tweak MESA_ENABLE_LLVM checks
Change the MESA_ENABLE_LLVM checks in Android.mk
files in order to get mesa3d to build w/ AOSP
using mmma.

This tries to re-create a change that was introduced
in the following merge in the AOSP branch:
  69f2c0128d2b Merge branch 'aosp/upstream-18.0'

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
Jason Ekstrand
9dbff6f6ce intel/iris: Always initialize CCS to 0
Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a
misunderstanding of the following lines in the bspec:

    The following are the general SW requirements for MCS buffer clear
    functionality:
        ...
         - If Software wants to enable Color Compression without Fast
           clear, Software needs to initialize MCS with zeros.
         - Lossless compression and CCS initialized to all F (using HW
           Fast Clear or SW direct Clear) on the same surface is not
           supported.

The first line does not refer to the CCS as the comment author supposed
but refers to the MCS as the comment says.  It means that if you want to
use MCS compression without a fast-clear, you should initialize the MCS
to 0x00.  This is because the value 0x00 in the MCS means "all data is
in plane 0" which is a perfectly valid non-fast-clear initialization.
It's also the value the MCS should be in if you do a RECTLIST slow-clear
where the primitive fully covers each pixel such that the same value is
written to all samples.

The second line in the above quote seems to imply that CCS fast-clear is
incompatible with MCS fast-clear.  In particular, MCS+CCS fast-clear
uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in
either the compressed or the pass-through state.  Therefore, we should
initialize the CCS to 0x00 even for MCS+CCS surfaces.

Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
2020-03-19 20:54:19 +00:00
Tomasz Pyra
36ec3cbcf8 gallium/swr: spin-lock performance improvement
Currently, the worker threads are very aggresively
polling for new tasks. If the work is not constantly
fed into the pipeline (which is a case for most of
interactive applications), this creates unnecessary
memory pressure and is using CPU cycles that
could otherwise be used by the applications.
The change implements simple back off mechanism
to help with this problem

Change by Tomasz Pyra (tomasz.pyra@intel.com)

Reviewed-by: Alok Hota <alok.hota@intel.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4226>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4226>
2020-03-19 11:11:26 +00:00
Jason Ekstrand
3fb8f19481 intel/blorp: Add support for swizzling fast-clear colors
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
2020-03-18 21:05:07 +00:00
Vasily Khoruzhick
0c41937440 lima: decode depth/stencil write bits in RSW
Now that we know the bits that are responsible for enabling depth/stencil
writes in shader we can decode them properly.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Icenowy Zheng
9205762cae lima: implement zsbuf reload
Fragment shader can write depth and stencil if we set necessary flags
in RSW. In addition to that we need to use special format for Z24S8.
Original format is apparently Z24X8 since we can't sample stencil in GLES2.
This new format also seems to use several components for storing depth
since we saw r != g != b when sampling with this format.

[vasily: - initialize clear->depth to 0xffffff if we reload depth, just
           like blob does. Reloading doesn't work otherwise
         - use single bitmap for reload type]

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Vasily Khoruzhick
dbceabed72 lima: disable Z16 format
Unfortunately we don't know how to reload Z16 buffers yet and blob
is using Z24 for dEQP tests that need depth reload.

Reviewed-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Eric Anholt
8b8af6d398 gallium/util: Switch util_float_to_half to _mesa_float_to_half()'s impl.
The util_float_to_half() implementation was much smaller, but when trying
to switch _mesa_float_to_half to it, many testcases
(dEQP-VK.spirv_assembly.instruction.graphics.opquantize.*,
piglit.spec.arb_shading_language_packing.*packhalf2x16) start failing on
Intel.  Replace the broken impl so that people don't have to debug it
later.

Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3699>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3699>
2020-03-17 22:28:12 +00:00
Dave Airlie
040ce9a1b3 gallium: fix build with latest meson and gcc10
In Fedora 32 build was failing with meson-0.53.2-1.git88e40c7.fc32
and gcc-10.0.1-0.9.fc32.x86_64.

Worked with meson-0.53.1-1 and same gcc.

/usr/bin/ld: src/gallium/state_trackers/dri/libdri.a(dri2.c.o): in function `dri2_interop_export_object':
/home/airlied/devel/mesa/mesa/build/../src/gallium/state_trackers/dri/dri2.c:1813: undefined reference to `st_finalize_texture'
/usr/bin/ld: src/gallium/state_trackers/dri/libdri.a(dri_screen.c.o): in function `dri_init_screen_helper':
/home/airlied/devel/mesa/mesa/build/../src/gallium/state_trackers/dri/dri_screen.c:580: undefined reference to `st_gl_api_create'

Moving this around seems to fix it.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4220>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4220>
2020-03-17 21:14:38 +00:00
Marek Olšák
56cc10bd27 ac: unify denorm setting enforcement
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
2020-03-17 20:47:48 +00:00
Marek Olšák
e4959add2f gallium/u_vbuf: simplify the first if statement in u_vbuf_upload_buffers
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
2020-03-17 19:13:57 +00:00
Marek Olšák
99a29a20d2 gallium/u_threaded: don't sync the thread for all unsychronized mappings
This was missing for the READ case. This improves glBegin/End performance.
(vbo maps with WRITE | READ | UNSYCHRONIZED)

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
2020-03-17 19:13:57 +00:00
Eric Anholt
5960dadd1f freedreno/a5xx: Fix min-vs-mag filtering decisions on non-mipmap tex.
This a port of 3338d6e5f8 ("freedreno/a3xx: Mostly fix min-vs-mag
filtering decisions on non-mipmap tex.")

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
2020-03-17 11:11:51 -07:00
Caio Marcelo de Oliveira Filho
3dd0d12aa5 intel/blorp: Plumb the stage through blorp upload_shader
Vulkan uses that for its own upload function -- even though for BLORP
it doesn't really currently care.  Neither Iris and i965 makes use of
it at the moment.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
2020-03-17 08:24:46 -07:00
Duncan Hopkins
4c35bc7e61 zink: zero out zink_render_pass_state
Since zink_render_pass_state is used as a hash-key, the entire struct gets
compared. This means we don't want any uninitialized padding in there, or
else we risk getting false negatives. This has led to issues on macOS builds.

So let's zero out the struct before we start filling it out.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4212>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4212>
2020-03-17 13:04:30 +00:00
Michel Dänzer
106bf59ca9 llvmpipe: Use uintptr_t for pointer values
Instead of uint64_t. Fixes potentially writing beyond the end of the
handles pointer array on 32-bit architectures (and copying all 0s
instead of the computed pointer values to the array on big endian
ones).

Corresponding compiler warning:

../src/gallium/drivers/llvmpipe/lp_state_cs.c: In function ‘llvmpipe_set_global_binding’:
../src/gallium/drivers/llvmpipe/lp_state_cs.c:1312:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
 1312 |       va = (uint64_t)((char *)lp_res->data + offset);
      |            ^

Fixes: 264663d55d "gallivm/llvmpipe: add support for global
                     operations."

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
2020-03-17 11:20:49 +01:00
Vasily Khoruzhick
ac1dbd5ef8 lima/gpir: fix crash in schedule_insert_ready_list()
Fix crash if node is already at position we want. Otherwise we remove
it from list (and list->prev becomes NULL) and then we dereference list->prev
in list_addtail()

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
2020-03-16 16:28:33 -07:00