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freedreno/registers: more GRAS_CL_CNTL bits, Z_CLAMP

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Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
This commit is contained in:
Jonathan Marek 2020-03-23 21:21:11 -04:00 • committed by Marge Bot
parent 43918c9a7f
commit 07a8100aed
3 changed files with 20 additions and 6 deletions
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20
src/freedreno/registers/a6xx.xml
View file

@ -1821,9 +1821,14 @@ to upconvert to 32b float internally?
<!-- always 0x03200000 ? -->
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
<reg32 offset="0x8000" name="GRAS_DISABLE_CNTL">
<!-- likely something clip-disable related -->
<bitfield name="UNK0" pos="0" type="boolean"/>
<reg32 offset="0x8000" name="GRAS_CL_CNTL">
<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
<bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
<bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
<!-- set with depthClampEnable, not clear what it does -->
<bitfield name="UNK5" pos="5" type="boolean"/>
<!-- controls near z clip behavior (set for vulkan) -->
<bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
<!-- guess based on a3xx and meaning of bits 8 and 9
if the guess is right then this is related to point sprite clipping -->
<bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
@ -1876,6 +1881,10 @@ to upconvert to 32b float internally?
<reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
<reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
<!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
<reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
<reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
<reg32 offset="0x8090" name="GRAS_SU_CNTL">
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
@ -2209,6 +2218,7 @@ to upconvert to 32b float internally?
<bitfield name="Z_ENABLE" pos="0" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
<doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
<bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
</reg32>
@ -2286,6 +2296,10 @@ to upconvert to 32b float internally?
<bitfield name="ENABLE" pos="0" type="boolean"/>
</reg32>
<!-- clamps depth value for depth test/write -->
<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>

4
src/freedreno/vulkan/tu_pipeline.c
View file

@ -1342,8 +1342,8 @@ tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
static void
tu6_emit_gras_unknowns(struct tu_cs *cs)
{
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DISABLE_CNTL, 1);
tu_cs_emit(cs, A6XX_GRAS_DISABLE_CNTL_VP_CLIP_CODE_IGNORE);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_CNTL, 1);
tu_cs_emit(cs, A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
tu_cs_emit(cs, 0x0);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);

2
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
View file

@ -52,7 +52,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
}
OUT_REG(ring,
A6XX_GRAS_DISABLE_CNTL(.vp_clip_code_ignore = 1),
A6XX_GRAS_CL_CNTL(.vp_clip_code_ignore = 1),
A6XX_GRAS_UNKNOWN_8001());
OUT_REG(ring,