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winsys/radeon: change to 3-space indentation

Browse source 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
This commit is contained in:
Marek Olšák 2020-03-13 16:10:56 -04:00
parent b13d5265cc
commit 7a59d6eaa2
8 changed files with 2622 additions and 2629 deletions
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3
src/gallium/winsys/radeon/drm/.editorconfig
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@ -1,3 +0,0 @@
[*.{c,h}]
indent_style = space
indent_size = 4

1878
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
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File diff suppressed because it is too large Load diff

66
src/gallium/winsys/radeon/drm/radeon_drm_bo.h
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@ -33,47 +33,47 @@
#include "pipebuffer/pb_slab.h"
struct radeon_bo {
struct pb_buffer base;
union {
struct {
struct pb_cache_entry cache_entry;
struct pb_buffer base;
union {
struct {
struct pb_cache_entry cache_entry;
void *ptr;
mtx_t map_mutex;
unsigned map_count;
bool use_reusable_pool;
} real;
struct {
struct pb_slab_entry entry;
struct radeon_bo *real;
void *ptr;
mtx_t map_mutex;
unsigned map_count;
bool use_reusable_pool;
} real;
struct {
struct pb_slab_entry entry;
struct radeon_bo *real;
unsigned num_fences;
unsigned max_fences;
struct radeon_bo **fences;
} slab;
} u;
unsigned num_fences;
unsigned max_fences;
struct radeon_bo **fences;
} slab;
} u;
struct radeon_drm_winsys *rws;
void *user_ptr; /* from buffer_from_ptr */
struct radeon_drm_winsys *rws;
void *user_ptr; /* from buffer_from_ptr */
uint32_t handle; /* 0 for slab entries */
uint32_t flink_name;
uint64_t va;
uint32_t hash;
enum radeon_bo_domain initial_domain;
uint32_t handle; /* 0 for slab entries */
uint32_t flink_name;
uint64_t va;
uint32_t hash;
enum radeon_bo_domain initial_domain;
/* how many command streams is this bo referenced in? */
int num_cs_references;
/* how many command streams is this bo referenced in? */
int num_cs_references;
/* how many command streams, which are being emitted in a separate
* thread, is this bo referenced in? */
int num_active_ioctls;
/* how many command streams, which are being emitted in a separate
* thread, is this bo referenced in? */
int num_active_ioctls;
};
struct radeon_slab {
struct pb_slab base;
struct radeon_bo *buffer;
struct radeon_bo *entries;
struct pb_slab base;
struct radeon_bo *buffer;
struct radeon_bo *entries;
};
void radeon_bo_destroy(struct pb_buffer *_buf);
@ -89,7 +89,7 @@ void radeon_bo_slab_free(void *priv, struct pb_slab *slab);
static inline
void radeon_bo_reference(struct radeon_bo **dst, struct radeon_bo *src)
{
pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src);
pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src);
}
void *radeon_bo_do_map(struct radeon_bo *bo);

1033
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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File diff suppressed because it is too large Load diff

114
src/gallium/winsys/radeon/drm/radeon_drm_cs.h
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@ -35,63 +35,63 @@ struct radeon_ctx {
};
struct radeon_bo_item {
struct radeon_bo *bo;
union {
struct {
uint32_t priority_usage;
} real;
struct {
unsigned real_idx;
} slab;
} u;
struct radeon_bo *bo;
union {
struct {
uint32_t priority_usage;
} real;
struct {
unsigned real_idx;
} slab;
} u;
};
struct radeon_cs_context {
uint32_t buf[16 * 1024];
uint32_t buf[16 * 1024];
int fd;
struct drm_radeon_cs cs;
struct drm_radeon_cs_chunk chunks[3];
uint64_t chunk_array[3];
uint32_t flags[2];
int fd;
struct drm_radeon_cs cs;
struct drm_radeon_cs_chunk chunks[3];
uint64_t chunk_array[3];
uint32_t flags[2];
/* Buffers. */
unsigned max_relocs;
unsigned num_relocs;
unsigned num_validated_relocs;
struct radeon_bo_item *relocs_bo;
struct drm_radeon_cs_reloc *relocs;
/* Buffers. */
unsigned max_relocs;
unsigned num_relocs;
unsigned num_validated_relocs;
struct radeon_bo_item *relocs_bo;
struct drm_radeon_cs_reloc *relocs;
unsigned num_slab_buffers;
unsigned max_slab_buffers;
struct radeon_bo_item *slab_buffers;
unsigned num_slab_buffers;
unsigned max_slab_buffers;
struct radeon_bo_item *slab_buffers;
int reloc_indices_hashlist[4096];
int reloc_indices_hashlist[4096];
};
struct radeon_drm_cs {
struct radeon_cmdbuf base;
enum ring_type ring_type;
struct radeon_cmdbuf base;
enum ring_type ring_type;
/* We flip between these two CS. While one is being consumed
* by the kernel in another thread, the other one is being filled
* by the pipe driver. */
struct radeon_cs_context csc1;
struct radeon_cs_context csc2;
/* The currently-used CS. */
struct radeon_cs_context *csc;
/* The CS being currently-owned by the other thread. */
struct radeon_cs_context *cst;
/* We flip between these two CS. While one is being consumed
* by the kernel in another thread, the other one is being filled
* by the pipe driver. */
struct radeon_cs_context csc1;
struct radeon_cs_context csc2;
/* The currently-used CS. */
struct radeon_cs_context *csc;
/* The CS being currently-owned by the other thread. */
struct radeon_cs_context *cst;
/* The winsys. */
struct radeon_drm_winsys *ws;
/* The winsys. */
struct radeon_drm_winsys *ws;
/* Flush CS. */
void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
void *flush_data;
/* Flush CS. */
void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
void *flush_data;
struct util_queue_fence flush_completed;
struct pipe_fence_handle *next_fence;
struct util_queue_fence flush_completed;
struct pipe_fence_handle *next_fence;
};
int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo);
@ -99,41 +99,41 @@ int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo);
static inline struct radeon_drm_cs *
radeon_drm_cs(struct radeon_cmdbuf *base)
{
return (struct radeon_drm_cs*)base;
return (struct radeon_drm_cs*)base;
}
static inline bool
radeon_bo_is_referenced_by_cs(struct radeon_drm_cs *cs,
struct radeon_bo *bo)
{
int num_refs = bo->num_cs_references;
return num_refs == bo->rws->num_cs ||
(num_refs && radeon_lookup_buffer(cs->csc, bo) != -1);
int num_refs = bo->num_cs_references;
return num_refs == bo->rws->num_cs ||
(num_refs && radeon_lookup_buffer(cs->csc, bo) != -1);
}
static inline bool
radeon_bo_is_referenced_by_cs_for_write(struct radeon_drm_cs *cs,
struct radeon_bo *bo)
{
int index;
int index;
if (!bo->num_cs_references)
return false;
if (!bo->num_cs_references)
return false;
index = radeon_lookup_buffer(cs->csc, bo);
if (index == -1)
return false;
index = radeon_lookup_buffer(cs->csc, bo);
if (index == -1)
return false;
if (!bo->handle)
index = cs->csc->slab_buffers[index].u.slab.real_idx;
if (!bo->handle)
index = cs->csc->slab_buffers[index].u.slab.real_idx;
return cs->csc->relocs[index].write_domain != 0;
return cs->csc->relocs[index].write_domain != 0;
}
static inline bool
radeon_bo_is_referenced_by_any_cs(struct radeon_bo *bo)
{
return bo->num_cs_references != 0;
return bo->num_cs_references != 0;
}
void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs);

612
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View file

@ -30,16 +30,16 @@
static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
{
unsigned index, tileb;
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
tileb = MIN2(surf->u.legacy.tile_split, tileb);
tileb = 8 * 8 * surf->bpe;
tileb = MIN2(surf->u.legacy.tile_split, tileb);
for (index = 0; tileb > 64; index++)
tileb >>= 1;
for (index = 0; tileb > 64; index++)
tileb >>= 1;
assert(index < 16);
return index;
assert(index < 16);
return index;
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
@ -48,43 +48,43 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
static void set_micro_tile_mode(struct radeon_surf *surf,
struct radeon_info *info)
{
uint32_t tile_mode;
uint32_t tile_mode;
if (info->chip_class < GFX6) {
surf->micro_tile_mode = 0;
return;
}
if (info->chip_class < GFX6) {
surf->micro_tile_mode = 0;
return;
}
tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
if (info->chip_class >= GFX7)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
if (info->chip_class >= GFX7)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
}
static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
const struct legacy_surf_level *level_ws,
unsigned bpe)
{
level_drm->offset = level_ws->offset;
level_drm->slice_size = (uint64_t)level_ws->slice_size_dw * 4;
level_drm->nblk_x = level_ws->nblk_x;
level_drm->nblk_y = level_ws->nblk_y;
level_drm->pitch_bytes = level_ws->nblk_x * bpe;
level_drm->mode = level_ws->mode;
level_drm->offset = level_ws->offset;
level_drm->slice_size = (uint64_t)level_ws->slice_size_dw * 4;
level_drm->nblk_x = level_ws->nblk_x;
level_drm->nblk_y = level_ws->nblk_y;
level_drm->pitch_bytes = level_ws->nblk_x * bpe;
level_drm->mode = level_ws->mode;
}
static void surf_level_drm_to_winsys(struct legacy_surf_level *level_ws,
const struct radeon_surface_level *level_drm,
unsigned bpe)
{
level_ws->offset = level_drm->offset;
level_ws->slice_size_dw = level_drm->slice_size / 4;
level_ws->nblk_x = level_drm->nblk_x;
level_ws->nblk_y = level_drm->nblk_y;
level_ws->mode = level_drm->mode;
assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
level_ws->offset = level_drm->offset;
level_ws->slice_size_dw = level_drm->slice_size / 4;
level_ws->nblk_x = level_drm->nblk_x;
level_ws->nblk_y = level_drm->nblk_y;
level_ws->mode = level_drm->mode;
assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
}
static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
@ -93,257 +93,257 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
enum radeon_surf_mode mode,
const struct radeon_surf *surf_ws)
{
int i;
int i;
memset(surf_drm, 0, sizeof(*surf_drm));
memset(surf_drm, 0, sizeof(*surf_drm));
surf_drm->npix_x = tex->width0;
surf_drm->npix_y = tex->height0;
surf_drm->npix_z = tex->depth0;
surf_drm->blk_w = util_format_get_blockwidth(tex->format);
surf_drm->blk_h = util_format_get_blockheight(tex->format);
surf_drm->blk_d = 1;
surf_drm->array_size = 1;
surf_drm->last_level = tex->last_level;
surf_drm->bpe = bpe;
surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
surf_drm->npix_x = tex->width0;
surf_drm->npix_y = tex->height0;
surf_drm->npix_z = tex->depth0;
surf_drm->blk_w = util_format_get_blockwidth(tex->format);
surf_drm->blk_h = util_format_get_blockheight(tex->format);
surf_drm->blk_d = 1;
surf_drm->array_size = 1;
surf_drm->last_level = tex->last_level;
surf_drm->bpe = bpe;
surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
surf_drm->flags = flags;
surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
surf_drm->flags |= RADEON_SURF_SET(mode, MODE) |
RADEON_SURF_HAS_SBUFFER_MIPTREE |
RADEON_SURF_HAS_TILE_MODE_INDEX;
surf_drm->flags = flags;
surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
surf_drm->flags |= RADEON_SURF_SET(mode, MODE) |
RADEON_SURF_HAS_SBUFFER_MIPTREE |
RADEON_SURF_HAS_TILE_MODE_INDEX;
switch (tex->target) {
case PIPE_TEXTURE_1D:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
break;
case PIPE_TEXTURE_RECT:
case PIPE_TEXTURE_2D:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
break;
case PIPE_TEXTURE_3D:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
break;
case PIPE_TEXTURE_1D_ARRAY:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
surf_drm->array_size = tex->array_size;
break;
case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
assert(tex->array_size % 6 == 0);
/* fall through */
case PIPE_TEXTURE_2D_ARRAY:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
surf_drm->array_size = tex->array_size;
break;
case PIPE_TEXTURE_CUBE:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
break;
case PIPE_BUFFER:
default:
assert(0);
}
switch (tex->target) {
case PIPE_TEXTURE_1D:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
break;
case PIPE_TEXTURE_RECT:
case PIPE_TEXTURE_2D:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
break;
case PIPE_TEXTURE_3D:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
break;
case PIPE_TEXTURE_1D_ARRAY:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
surf_drm->array_size = tex->array_size;
break;
case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
assert(tex->array_size % 6 == 0);
/* fall through */
case PIPE_TEXTURE_2D_ARRAY:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
surf_drm->array_size = tex->array_size;
break;
case PIPE_TEXTURE_CUBE:
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
break;
case PIPE_BUFFER:
default:
assert(0);
}
surf_drm->bo_size = surf_ws->surf_size;
surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bo_size = surf_ws->surf_size;
surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bankw = surf_ws->u.legacy.bankw;
surf_drm->bankh = surf_ws->u.legacy.bankh;
surf_drm->mtilea = surf_ws->u.legacy.mtilea;
surf_drm->tile_split = surf_ws->u.legacy.tile_split;
surf_drm->bankw = surf_ws->u.legacy.bankw;
surf_drm->bankh = surf_ws->u.legacy.bankh;
surf_drm->mtilea = surf_ws->u.legacy.mtilea;
surf_drm->tile_split = surf_ws->u.legacy.tile_split;
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->u.legacy.level[i],
bpe * surf_drm->nsamples);
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->u.legacy.level[i],
bpe * surf_drm->nsamples);
surf_drm->tiling_index[i] = surf_ws->u.legacy.tiling_index[i];
}
surf_drm->tiling_index[i] = surf_ws->u.legacy.tiling_index[i];
}
if (flags & RADEON_SURF_SBUFFER) {
surf_drm->stencil_tile_split = surf_ws->u.legacy.stencil_tile_split;
if (flags & RADEON_SURF_SBUFFER) {
surf_drm->stencil_tile_split = surf_ws->u.legacy.stencil_tile_split;
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->u.legacy.stencil_level[i],
surf_drm->nsamples);
surf_drm->stencil_tiling_index[i] = surf_ws->u.legacy.stencil_tiling_index[i];
}
}
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->u.legacy.stencil_level[i],
surf_drm->nsamples);
surf_drm->stencil_tiling_index[i] = surf_ws->u.legacy.stencil_tiling_index[i];
}
}
}
static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
struct radeon_surf *surf_ws,
const struct radeon_surface *surf_drm)
{
int i;
int i;
memset(surf_ws, 0, sizeof(*surf_ws));
memset(surf_ws, 0, sizeof(*surf_ws));
surf_ws->blk_w = surf_drm->blk_w;
surf_ws->blk_h = surf_drm->blk_h;
surf_ws->bpe = surf_drm->bpe;
surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
surf_ws->has_stencil = !!(surf_drm->flags & RADEON_SURF_SBUFFER);
surf_ws->flags = surf_drm->flags;
surf_ws->blk_w = surf_drm->blk_w;
surf_ws->blk_h = surf_drm->blk_h;
surf_ws->bpe = surf_drm->bpe;
surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
surf_ws->has_stencil = !!(surf_drm->flags & RADEON_SURF_SBUFFER);
surf_ws->flags = surf_drm->flags;
surf_ws->surf_size = surf_drm->bo_size;
surf_ws->surf_alignment = surf_drm->bo_alignment;
surf_ws->surf_size = surf_drm->bo_size;
surf_ws->surf_alignment = surf_drm->bo_alignment;
surf_ws->u.legacy.bankw = surf_drm->bankw;
surf_ws->u.legacy.bankh = surf_drm->bankh;
surf_ws->u.legacy.mtilea = surf_drm->mtilea;
surf_ws->u.legacy.tile_split = surf_drm->tile_split;
surf_ws->u.legacy.bankw = surf_drm->bankw;
surf_ws->u.legacy.bankh = surf_drm->bankh;
surf_ws->u.legacy.mtilea = surf_drm->mtilea;
surf_ws->u.legacy.tile_split = surf_drm->tile_split;
surf_ws->u.legacy.macro_tile_index = cik_get_macro_tile_index(surf_ws);
surf_ws->u.legacy.macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->u.legacy.level[i], &surf_drm->level[i],
surf_drm->bpe * surf_drm->nsamples);
surf_ws->u.legacy.tiling_index[i] = surf_drm->tiling_index[i];
}
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->u.legacy.level[i], &surf_drm->level[i],
surf_drm->bpe * surf_drm->nsamples);
surf_ws->u.legacy.tiling_index[i] = surf_drm->tiling_index[i];
}
if (surf_ws->flags & RADEON_SURF_SBUFFER) {
surf_ws->u.legacy.stencil_tile_split = surf_drm->stencil_tile_split;
if (surf_ws->flags & RADEON_SURF_SBUFFER) {
surf_ws->u.legacy.stencil_tile_split = surf_drm->stencil_tile_split;
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->u.legacy.stencil_level[i],
&surf_drm->stencil_level[i],
surf_drm->nsamples);
surf_ws->u.legacy.stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
}
}
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->u.legacy.stencil_level[i],
&surf_drm->stencil_level[i],
surf_drm->nsamples);
surf_ws->u.legacy.stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
}
}
set_micro_tile_mode(surf_ws, &ws->info);
surf_ws->is_displayable = surf_ws->is_linear ||
surf_ws->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
surf_ws->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
set_micro_tile_mode(surf_ws, &ws->info);
surf_ws->is_displayable = surf_ws->is_linear ||
surf_ws->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
surf_ws->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
}
static void si_compute_cmask(const struct radeon_info *info,
const struct ac_surf_config *config,
struct radeon_surf *surf)
const struct ac_surf_config *config,
struct radeon_surf *surf)
{
unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
unsigned num_pipes = info->num_tile_pipes;
unsigned cl_width, cl_height;
unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
unsigned num_pipes = info->num_tile_pipes;
unsigned cl_width, cl_height;
if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
return;
if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
return;
assert(info->chip_class <= GFX8);
assert(info->chip_class <= GFX8);
switch (num_pipes) {
case 2:
cl_width = 32;
cl_height = 16;
break;
case 4:
cl_width = 32;
cl_height = 32;
break;
case 8:
cl_width = 64;
cl_height = 32;
break;
case 16: /* Hawaii */
cl_width = 64;
cl_height = 64;
break;
default:
assert(0);
return;
}
switch (num_pipes) {
case 2:
cl_width = 32;
cl_height = 16;
break;
case 4:
cl_width = 32;
cl_height = 32;
break;
case 8:
cl_width = 64;
cl_height = 32;
break;
case 16: /* Hawaii */
cl_width = 64;
cl_height = 64;
break;
default:
assert(0);
return;
}
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
if (surf->u.legacy.cmask_slice_tile_max)
surf->u.legacy.cmask_slice_tile_max -= 1;
surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
if (surf->u.legacy.cmask_slice_tile_max)
surf->u.legacy.cmask_slice_tile_max -= 1;
unsigned num_layers;
if (config->is_3d)
num_layers = config->info.depth;
else if (config->is_cube)
num_layers = 6;
else
num_layers = config->info.array_size;
unsigned num_layers;
if (config->is_3d)
num_layers = config->info.depth;
else if (config->is_cube)
num_layers = 6;
else
num_layers = config->info.array_size;
surf->cmask_alignment = MAX2(256, base_align);
surf->cmask_size = align(slice_bytes, base_align) * num_layers;
surf->cmask_alignment = MAX2(256, base_align);
surf->cmask_size = align(slice_bytes, base_align) * num_layers;
}
static void si_compute_htile(const struct radeon_info *info,
struct radeon_surf *surf, unsigned num_layers)
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = info->num_tile_pipes;
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = info->num_tile_pipes;
surf->htile_size = 0;
surf->htile_size = 0;
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) ||
surf->flags & RADEON_SURF_NO_HTILE)
return;
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) ||
surf->flags & RADEON_SURF_NO_HTILE)
return;
if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
!info->htile_cmask_support_1d_tiling)
return;
if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
!info->htile_cmask_support_1d_tiling)
return;
/* Overalign HTILE on P2 configs to work around GPU hangs in
/* Overalign HTILE on P2 configs to work around GPU hangs in
* piglit/depthstencil-render-miplevels 585.
*
* This has been confirmed to help Kabini & Stoney, where the hangs
* are always reproducible. I think I have seen the test hang
* on Carrizo too, though it was very rare there.
*/
if (info->chip_class >= GFX7 && num_pipes < 4)
num_pipes = 4;
if (info->chip_class >= GFX7 && num_pipes < 4)
num_pipes = 4;
switch (num_pipes) {
case 1:
cl_width = 32;
cl_height = 16;
break;
case 2:
cl_width = 32;
cl_height = 32;
break;
case 4:
cl_width = 64;
cl_height = 32;
break;
case 8:
cl_width = 64;
cl_height = 64;
break;
case 16:
cl_width = 128;
cl_height = 64;
break;
default:
assert(0);
return;
}
switch (num_pipes) {
case 1:
cl_width = 32;
cl_height = 16;
break;
case 2:
cl_width = 32;
cl_height = 32;
break;
case 4:
cl_width = 64;
cl_height = 32;
break;
case 8:
cl_width = 64;
cl_height = 64;
break;
case 16:
cl_width = 128;
cl_height = 64;
break;
default:
assert(0);
return;
}
width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
pipe_interleave_bytes = info->pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
pipe_interleave_bytes = info->pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
surf->htile_alignment = base_align;
surf->htile_size = num_layers * align(slice_bytes, base_align);
surf->htile_alignment = base_align;
surf->htile_size = num_layers * align(slice_bytes, base_align);
}
static int radeon_winsys_surface_init(struct radeon_winsys *rws,
@ -352,114 +352,114 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
enum radeon_surf_mode mode,
struct radeon_surf *surf_ws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
struct radeon_surface surf_drm;
int r;
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
struct radeon_surface surf_drm;
int r;
surf_winsys_to_drm(&surf_drm, tex, flags, bpe, mode, surf_ws);
surf_winsys_to_drm(&surf_drm, tex, flags, bpe, mode, surf_ws);
if (!(flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FMASK))) {
r = radeon_surface_best(ws->surf_man, &surf_drm);
if (r)
return r;
}
if (!(flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FMASK))) {
r = radeon_surface_best(ws->surf_man, &surf_drm);
if (r)
return r;
}
r = radeon_surface_init(ws->surf_man, &surf_drm);
if (r)
return r;
r = radeon_surface_init(ws->surf_man, &surf_drm);
if (r)
return r;
surf_drm_to_winsys(ws, surf_ws, &surf_drm);
surf_drm_to_winsys(ws, surf_ws, &surf_drm);
/* Compute FMASK. */
if (ws->gen == DRV_SI &&
tex->nr_samples >= 2 &&
!(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK | RADEON_SURF_NO_FMASK))) {
/* FMASK is allocated like an ordinary texture. */
struct pipe_resource templ = *tex;
struct radeon_surf fmask = {};
unsigned fmask_flags, bpe;
/* Compute FMASK. */
if (ws->gen == DRV_SI &&
tex->nr_samples >= 2 &&
!(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK | RADEON_SURF_NO_FMASK))) {
/* FMASK is allocated like an ordinary texture. */
struct pipe_resource templ = *tex;
struct radeon_surf fmask = {};
unsigned fmask_flags, bpe;
templ.nr_samples = 1;
fmask_flags = flags | RADEON_SURF_FMASK;
templ.nr_samples = 1;
fmask_flags = flags | RADEON_SURF_FMASK;
switch (tex->nr_samples) {
case 2:
case 4:
bpe = 1;
break;
case 8:
bpe = 4;
break;
default:
fprintf(stderr, "radeon: Invalid sample count for FMASK allocation.\n");
return -1;
}
switch (tex->nr_samples) {
case 2:
case 4:
bpe = 1;
break;
case 8:
bpe = 4;
break;
default:
fprintf(stderr, "radeon: Invalid sample count for FMASK allocation.\n");
return -1;
}
if (radeon_winsys_surface_init(rws, &templ, fmask_flags, bpe,
RADEON_SURF_MODE_2D, &fmask)) {
fprintf(stderr, "Got error in surface_init while allocating FMASK.\n");
return -1;
}
if (radeon_winsys_surface_init(rws, &templ, fmask_flags, bpe,
RADEON_SURF_MODE_2D, &fmask)) {
fprintf(stderr, "Got error in surface_init while allocating FMASK.\n");
return -1;
}
assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
surf_ws->fmask_size = fmask.surf_size;
surf_ws->fmask_alignment = MAX2(256, fmask.surf_alignment);
surf_ws->fmask_tile_swizzle = fmask.tile_swizzle;
surf_ws->fmask_size = fmask.surf_size;
surf_ws->fmask_alignment = MAX2(256, fmask.surf_alignment);
surf_ws->fmask_tile_swizzle = fmask.tile_swizzle;
surf_ws->u.legacy.fmask.slice_tile_max =
surf_ws->u.legacy.fmask.slice_tile_max =
(fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
if (surf_ws->u.legacy.fmask.slice_tile_max)
surf_ws->u.legacy.fmask.slice_tile_max -= 1;
if (surf_ws->u.legacy.fmask.slice_tile_max)
surf_ws->u.legacy.fmask.slice_tile_max -= 1;
surf_ws->u.legacy.fmask.tiling_index = fmask.u.legacy.tiling_index[0];
surf_ws->u.legacy.fmask.bankh = fmask.u.legacy.bankh;
surf_ws->u.legacy.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
}
surf_ws->u.legacy.fmask.tiling_index = fmask.u.legacy.tiling_index[0];
surf_ws->u.legacy.fmask.bankh = fmask.u.legacy.bankh;
surf_ws->u.legacy.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
}
if (ws->gen == DRV_SI &&
(tex->nr_samples <= 1 || surf_ws->fmask_size)) {
struct ac_surf_config config;
if (ws->gen == DRV_SI &&
(tex->nr_samples <= 1 || surf_ws->fmask_size)) {
struct ac_surf_config config;
/* Only these fields need to be set for the CMASK computation. */
config.info.width = tex->width0;
config.info.height = tex->height0;
config.info.depth = tex->depth0;
config.info.array_size = tex->array_size;
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
/* Only these fields need to be set for the CMASK computation. */
config.info.width = tex->width0;
config.info.height = tex->height0;
config.info.depth = tex->depth0;
config.info.array_size = tex->array_size;
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
si_compute_cmask(&ws->info, &config, surf_ws);
}
si_compute_cmask(&ws->info, &config, surf_ws);
}
if (ws->gen == DRV_SI) {
si_compute_htile(&ws->info, surf_ws, util_num_layers(tex, 0));
if (ws->gen == DRV_SI) {
si_compute_htile(&ws->info, surf_ws, util_num_layers(tex, 0));
/* Determine the memory layout of multiple allocations in one buffer. */
surf_ws->total_size = surf_ws->surf_size;
/* Determine the memory layout of multiple allocations in one buffer. */
surf_ws->total_size = surf_ws->surf_size;
if (surf_ws->htile_size) {
surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment);
surf_ws->total_size = surf_ws->htile_offset + surf_ws->htile_size;
}
if (surf_ws->htile_size) {
surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment);
surf_ws->total_size = surf_ws->htile_offset + surf_ws->htile_size;
}
if (surf_ws->fmask_size) {
assert(tex->nr_samples >= 2);
surf_ws->fmask_offset = align64(surf_ws->total_size, surf_ws->fmask_alignment);
surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
}
if (surf_ws->fmask_size) {
assert(tex->nr_samples >= 2);
surf_ws->fmask_offset = align64(surf_ws->total_size, surf_ws->fmask_alignment);
surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
}
/* Single-sample CMASK is in a separate buffer. */
if (surf_ws->cmask_size && tex->nr_samples >= 2) {
surf_ws->cmask_offset = align64(surf_ws->total_size, surf_ws->cmask_alignment);
surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size;
}
}
/* Single-sample CMASK is in a separate buffer. */
if (surf_ws->cmask_size && tex->nr_samples >= 2) {
surf_ws->cmask_offset = align64(surf_ws->total_size, surf_ws->cmask_alignment);
surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size;
}
}
return 0;
return 0;
}
void radeon_surface_init_functions(struct radeon_drm_winsys *ws)
{
ws->base.surface_init = radeon_winsys_surface_init;
ws->base.surface_init = radeon_winsys_surface_init;
}

1448
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

File diff suppressed because it is too large Load diff

97
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
View file

@ -37,76 +37,75 @@
struct radeon_drm_cs;
enum radeon_generation {
DRV_R300,
DRV_R600,
DRV_SI
DRV_R300,
DRV_R600,
DRV_SI
};
#define RADEON_SLAB_MIN_SIZE_LOG2 9
#define RADEON_SLAB_MAX_SIZE_LOG2 14
struct radeon_vm_heap {
mtx_t mutex;
uint64_t start;
uint64_t end;
struct list_head holes;
mtx_t mutex;
uint64_t start;
uint64_t end;
struct list_head holes;
};
struct radeon_drm_winsys {
struct radeon_winsys base;
struct pipe_reference reference;
struct pb_cache bo_cache;
struct pb_slabs bo_slabs;
struct radeon_winsys base;
struct pipe_reference reference;
struct pb_cache bo_cache;
struct pb_slabs bo_slabs;
int fd; /* DRM file descriptor */
int num_cs; /* The number of command streams created. */
uint64_t allocated_vram;
uint64_t allocated_gtt;
uint64_t mapped_vram;
uint64_t mapped_gtt;
uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
uint64_t num_gfx_IBs;
uint64_t num_sdma_IBs;
uint64_t num_mapped_buffers;
uint32_t next_bo_hash;
int fd; /* DRM file descriptor */
int num_cs; /* The number of command streams created. */
uint64_t allocated_vram;
uint64_t allocated_gtt;
uint64_t mapped_vram;
uint64_t mapped_gtt;
uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
uint64_t num_gfx_IBs;
uint64_t num_sdma_IBs;
uint64_t num_mapped_buffers;
uint32_t next_bo_hash;
enum radeon_generation gen;
struct radeon_info info;
uint32_t va_start;
uint32_t va_unmap_working;
uint32_t accel_working2;
enum radeon_generation gen;
struct radeon_info info;
uint32_t va_start;
uint32_t va_unmap_working;
uint32_t accel_working2;
/* List of buffer GEM names. Protected by bo_handles_mutex. */
struct hash_table *bo_names;
/* List of buffer handles. Protectded by bo_handles_mutex. */
struct hash_table *bo_handles;
/* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
struct hash_table *bo_vas;
mtx_t bo_handles_mutex;
mtx_t bo_fence_lock;
/* List of buffer GEM names. Protected by bo_handles_mutex. */
struct hash_table *bo_names;
/* List of buffer handles. Protectded by bo_handles_mutex. */
struct hash_table *bo_handles;
/* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
struct hash_table *bo_vas;
mtx_t bo_handles_mutex;
mtx_t bo_fence_lock;
struct radeon_vm_heap vm32;
struct radeon_vm_heap vm64;
struct radeon_vm_heap vm32;
struct radeon_vm_heap vm64;
bool check_vm;
bool check_vm;
struct radeon_surface_manager *surf_man;
struct radeon_surface_manager *surf_man;
uint32_t num_cpus; /* Number of CPUs. */
uint32_t num_cpus; /* Number of CPUs. */
struct radeon_drm_cs *hyperz_owner;
mtx_t hyperz_owner_mutex;
struct radeon_drm_cs *cmask_owner;
mtx_t cmask_owner_mutex;
struct radeon_drm_cs *hyperz_owner;
mtx_t hyperz_owner_mutex;
struct radeon_drm_cs *cmask_owner;
mtx_t cmask_owner_mutex;
/* multithreaded command submission */
struct util_queue cs_queue;
/* multithreaded command submission */
struct util_queue cs_queue;
};
static inline struct radeon_drm_winsys *
radeon_drm_winsys(struct radeon_winsys *base)
static inline struct radeon_drm_winsys *radeon_drm_winsys(struct radeon_winsys *base)
{
return (struct radeon_drm_winsys*)base;
return (struct radeon_drm_winsys*)base;
}
uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws);