Commit graph

114289 commits

Author SHA1 Message Date
Dave Airlie
ee90339cfb llvmpipe: add gl_SampleMaskIn support.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
310823eccd gallivm/nir: add sample_mask_in support
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
0dac24790e llvmpipe/fs: hook up the interpolation APIs.
This hooks the nir code to the interp code.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
3f71a5e25f llvmpipe: add interp instruction support
This allows interpolating an attribute at offset/sample/centroid
locations.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
06c10fa3a5 llvmpipe/interp: refactor out centroid calculations
These will be reused in the interp instruction code.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
c1f5a23a4d llvmpipe/interp: refactor out use of pixel center offset
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
ae5f6ddc05 gallivm/nir: add an interpolation interface.
This supports interpolating at a certain location, offsets,
sample or centroid.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
53fcb30c12 llvmpipe: remove non-simple interpolation paths.
These are broken since adding multisample, and unused for
quite a while.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
6b7e03175d llvmpipe/interp: fix interpolating frag pos for sample shading
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
c9690b7471 llvmpipe: use per-sample position not sample id for interp
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
5098764483 llvmpipe: don't use sample mask with 0 samples
piglit:
spec/arb_sample_shading/builtin-gl-sample-mask 0
spec/arb_sample_shading/builtin-gl-sample-mask-simple 0
CTS:
KHR-GL45.sample_variables.mask.rgba8.samples_0.mask_zero

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5050>
2020-05-19 10:26:46 +10:00
Dave Airlie
b11aa12253 r600/sfn: add emit if start cayman support
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5084>
2020-05-18 21:56:29 +00:00
Dave Airlie
4746796b82 r600/sfn: add callstack non-evergreen support
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5084>
2020-05-18 21:56:29 +00:00
Dave Airlie
19273fb227 r600/sfn: cayman fix int trans op2
Fix integer multiplies

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5084>
2020-05-18 21:56:29 +00:00
Dave Airlie
38560e0d1d r600/sfn: fix cayman float instruction emission.
This is enough to get glxgears working.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5084>
2020-05-18 21:56:29 +00:00
Dave Airlie
ff9c95421a r600/sfn: plumb the chip class into the instruction emission
In order to emit the correct instruction sequences for cayman
we need this info.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5084>
2020-05-18 21:56:29 +00:00
Jason Ekstrand
164aed6c81 anv:gpu_memcpy: Emit 3DSTATE_VF_INDEXING on Gen8+
If this gets run right after something which uses
VK_VERTEX_INPUT_RATE_INSTANCE on its first vertex binding, we could end
up in serious trouble.

Fixes: 3d9747780b "anv: Add a helper for doing buffer copies with..."

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5090>
2020-05-18 21:42:05 +00:00
Caio Marcelo de Oliveira Filho
6a6c36e977 intel/fs: Use writes_memory from shader_info
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4815>
2020-05-18 21:09:17 +00:00
Caio Marcelo de Oliveira Filho
d89c28d314 nir: Use deref intrinsics to set writes_memory when gathering info
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4815>
2020-05-18 21:09:17 +00:00
Dave Airlie
d50069ab08 r600: enable TEXCOORD semantic for TGSI.
This should make intergrating with NIR easier

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5083>
2020-05-18 20:01:25 +00:00
Chris Wilson
34195d69dd iris: Initialise stub iris_seqno to 0
We create a stub never-signaled seqno to force the iris_fence to use the
fence fd, but we need to fully initialise the iris_seqno struct so that
the unset pointers are NULL and we do not try to destroy them later.

  ==38644== Conditional jump or move depends on uninitialised value(s)
  ==38644==    at 0xF7FBFAA: pipe_resource_reference (u_inlines.h:142)
  ==38644==    by 0xF7FC22F: iris_seqno_destroy (iris_seqno.c:38)
  ==38644==    by 0xF7E8930: iris_seqno_reference (iris_seqno.h:89)
  ==38644==    by 0xF7E8BC3: iris_fence_destroy (iris_fence.c:131)
  ==38644==    by 0xF7E8C41: iris_fence_reference (iris_fence.c:143)
  ==38644==    by 0xEF24525: dri2_destroy_fence (dri_helpers.c:176)
  ==38644==    by 0x4865DC2: dri2_egl_unref_sync (egl_dri2.c:3302)
  ==38644==    by 0x48661E8: dri2_destroy_sync (egl_dri2.c:3433)
  ==38644==    by 0x4855BA4: _eglDestroySync (eglapi.c:1952)
  ==38644==    by 0x4855CF5: eglDestroySyncKHR (eglapi.c:1972)
  ==38644==    by 0x402628: test_cleanup (egl_khr_fence_sync.c:232)
  ==38644==    by 0x40421E: test_eglCreateSyncKHR_native_from_fd (egl_khr_fence_sync.c:1521)

Closes: #2909
Fixes: fd1907efb3 ("iris: Convert fences to using lightweight seqno")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5004>
2020-05-18 19:22:12 +00:00
Rob Clark
a6184eae31 freedreno/drm: handle ancient kernels
Older kernels did not support `MSM_INFO_GET_IOVA`.  But this is only
required for (a) clover (ie. `fd_set_global_binding()`) and drm paths
that are limited to newer kernels.  So move the location of the assert
to fix new userspace on old kernels.

Fixes: c9e8df61dc ("freedreno: Initialize the bo's iova at creation time.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5081>
2020-05-18 19:00:47 +00:00
Rob Clark
106c2a65db freedreno/drm: don't pass thru 'DUMP' flag on older kernels
"softpin" mode was introduced in the same kernel as the 'DUMP' flag.  So
if we are using the legacy non-softpin path, clear the dump flag.  OTOH
the 'DUMP' flag isn't quite so needed on older kernels, since we would
get all cmdstream, even SDS stateobjs, dumped regardless, as they would
have cmd table entries.

Fixes: b2c23b1e48 ("freedreno: Mark all ringbuffer BOs as to be dumped on crash.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5081>
2020-05-18 19:00:47 +00:00
Ilia Mirkin
e422f61e6e freedreno/a3xx: fix rasterizer discard
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5080>
2020-05-18 18:34:04 +00:00
Rob Clark
5e10506834 freedreno/fdperf: add dependency on generated headers
To fix an issue reported here:
https://bugs.chromium.org/p/chromium/issues/detail?id=1083815

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5088>
2020-05-18 17:53:45 +00:00
Lucas Stach
78c46c2126 etnaviv: don't expose timer queries
We don't support any timer queries, so stop lying about our
ability to do so.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5086>
2020-05-18 17:03:05 +02:00
Ilia Mirkin
b5accb3ff9 freedreno/a3xx: parameterize ubo optimization
A3xx apparently has higher alignment requirements than later gens for
indirect const uploads. It also has fewer of them. Add compiler
parameters for both settings, and set accordingly for a3xx and a4xx+.
This fixes all the ubo test failures caused by this optimization.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
2020-05-17 19:51:40 -04:00
Ilia Mirkin
475fb28377 freedreno: fix off-by-one in assertions checking for const sizes
Caused assertions to trip even though everything was fine. The number of
constants can be equal to length, so we need less-than-or-equal.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
2020-05-17 19:51:36 -04:00
Ilia Mirkin
1c05e16666 freedreno/a3xx: fix const footprint
In commit 5d8f40a53a, the change was done incorrectly, switching from
max_const to constlen + 1. Instead it should have been constlen - 1,
which is the analog to the former max_const.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
2020-05-17 19:51:10 -04:00
Ilia Mirkin
9048adbd24 freedreno/ir3: avoid applying (sat) on bary.f
This causes failures on a3xx resulting in the non-sensical dEQP failures
on packUnorm2x16. The same test uses ldlv on a4xx+, so just disallow
(sat) on bary.f on all generations.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5074>
2020-05-17 21:17:57 +00:00
Ilia Mirkin
8d86892ea3 freedreno/a3xx: reinstate rgb10_a2ui texture format
Rendering doesn't work, but having the format in place avoids an assert
when selecting the texture format in st_format. I believe it's required
for GLES3, so more tracing is required to determine what bit we're
missing to make rendering work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5073>
2020-05-17 14:39:42 -04:00
Ilia Mirkin
ff4df32fae freedreno/a3xx: there's no r8i/ui rb format, only rg8i/rg8ui
This fixes a number of dEQP tests:

  dEQP-GLES3.functional.fbo.blit.conversion.r8*
  dEQP-GLES3.texture.specification.basic_teximage2d.r8*

and others. The reason why this enum showed up in traces for R8 is that
it was an "upgraded" texture to R8G8.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5073>
2020-05-17 14:39:42 -04:00
Christopher Egert
78615dcca1 radv: use util_float_to_half_rtz
Since commit 8b8af6d398 there is a
performance regression in dirt 4 on picasso APUs.

The game ends up feeding a large value into this which overflows on the
conversion to 16bit float. With the old implementation (which now lives
in util_float_to_half_rtz) it would be clamped to inf-1, while the new
one returns inf. This causes a performance hit somehow at some point
down the line.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 8b8af6d398 "gallium/util: Switch util_float_to_half to _mesa_float_to_half()'s impl."
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5062>
2020-05-17 01:12:59 +02:00
Erico Nunes
632a921bd0 lima/ppir: optimize tex loads with single successor
These don't need a mov, and can be used directly with pipeline output.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
2020-05-16 17:24:03 +02:00
Erico Nunes
a4b7699d84 lima/ppir: rework tex lowering
Move steps from lowering to emit, since they can be done earlier in a
single place, rather than in two-steps.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
2020-05-16 17:24:00 +02:00
Erico Nunes
92611e21c1 lima/ppir: improve handling for successors in other blocks
ppir doesn't register successors in other blocks, and causes
ppir_node_has_single_succ to be unreliable as it might return true for
nodes with successors in other blocks.
This is bad for optimization passes that try to pipeline registers or
avoid insertion of movs, as that can generally only be done for nodes
with a single user.
As of now, ppir can't just start adding successors in other blocks as
that breaks the scheduling code.
So this patch is a little hacky but enables pipelining optimizations
during lowering. It can hopefully be removed during future scheduler
rework.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
2020-05-16 17:23:58 +02:00
Erico Nunes
96c1d5f629 lima/ppir: handle failures on all ppir_emit_cf_list paths
In some paths where ppir_emit_cf_list is called, compilation errors such
as in unsupported features were not being handled, allowing compilation
to continue and fail at some random point later.
Handle them properly so compilation aborts in the expected way rather
than what may look like a compiler crash/bug.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
2020-05-16 17:23:48 +02:00
Eric Engestrom
fa3549c92b util/rand_xor: extend the urandom path to all non-Windows platforms
Any system that provides `/dev/urandom` should be allowed to try to use it.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2316>
2020-05-16 12:05:37 +00:00
Eric Engestrom
d76abe98cf util/rand_xor: fallback Linux to time-based instead of fixed seed
When the caller asked for a randomised_seed, we should fall back to the
time-based seed instead of the fixed seed.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2316>
2020-05-16 12:05:37 +00:00
Eric Engestrom
e0ce684aae util/rand_xor: drop unused header
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2316>
2020-05-16 12:05:37 +00:00
Eric Engestrom
f50f26325f util/rand_xor: make it clear that {,s_}rand_xorshift128plus take *exactly 2* uint64_t
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2316>
2020-05-16 12:05:37 +00:00
Thong Thai
494b7ef0c1 gallium/auxiliary/vl: Fix compute shader scaling for non-square pixels
Calculate the scale_y parameter instead of assuming square pixels.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5057>
2020-05-16 02:17:26 +00:00
Marek Olšák
fd6a5e112a gallium/u_threaded: execute transfer_unmap with THREAD_SAFE directly
This was the original intention, but it wasn't fully implemented.

Fixes: 7f22e0fd29

Closes: #2953

Tested by: John Galt <johngalt@fake.mail>

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5030>
2020-05-15 22:26:52 +00:00
Marek Olšák
c9ccceff10 radeonsi: test uncached clear/copy buffer performance with compute shaders
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák
5acf99e81f radeonsi: compute perf tests - don't test 1 wave/SA limit, test no limit first
1 wave/SA is always slow and thus not useful

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák
c45a2145f5 radeonsi: disable the L2 cache for CPU read mappings of buffers
for faster copying over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák
7356144fe4 radeonsi: disable the L2 cache for most CPU mappings of textures
for faster blits over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák
36c0124804 winsys/amdgpu: add RADEON_FLAG_UNCACHED for faster blits over PCIe
Small blits benefit more. Good access pattern is required.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák
cbbc18bc67 radeonsi: use display_dcc_offset for setting displayable_dcc_cb_mask
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00
Marek Olšák
b5ac9d18d8 radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
2020-05-15 22:12:35 +00:00