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radeonsi: disable the L2 cache for most CPU mappings of textures

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for faster blits over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
This commit is contained in:
Marek Olšák 2020-05-06 14:51:50 -04:00 • committed by Marge Bot
parent 36c0124804
commit 7356144fe4
3 changed files with 25 additions and 2 deletions
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8
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -182,6 +182,14 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
res->flags |= RADEON_FLAG_32BIT;
/* For higher throughput and lower latency over PCIe assuming sequential access.
* Only CP DMA, SDMA, and optimized compute benefit from this.
* GFX8 and older don't support RADEON_FLAG_UNCACHED.
*/
if (sscreen->info.chip_class >= GFX9 &&
res->b.b.flags & SI_RESOURCE_FLAG_UNCACHED)
res->flags |= RADEON_FLAG_UNCACHED;
/* Set expected VRAM and GART usage for the buffer. */
res->vram_usage = 0;
res->gart_usage = 0;

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -122,6 +122,7 @@
(((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
(((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
#define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
enum si_clear_code
{

18
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -1694,10 +1694,24 @@ static void *si_texture_transfer_map(struct pipe_context *ctx, struct pipe_resou
if (use_staging_texture) {
struct pipe_resource resource;
struct si_texture *staging;
unsigned bo_usage = usage & PIPE_TRANSFER_READ ? PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
unsigned bo_flags = SI_RESOURCE_FLAG_FORCE_LINEAR;
/* The pixel shader has a bad access pattern for linear textures.
* If a pixel shader is used to blit to/from staging, don't disable caches.
*
* MSAA, depth/stencil textures, and compressed textures use the pixel shader
* to blit.
*/
if (texture->nr_samples <= 1 &&
!tex->is_depth &&
!util_format_is_compressed(texture->format) &&
/* Texture uploads with DCC use the pixel shader to blit */
(!(usage & PIPE_TRANSFER_WRITE) || !vi_dcc_enabled(tex, level)))
bo_flags |= SI_RESOURCE_FLAG_UNCACHED;
si_init_temp_resource_from_box(&resource, texture, box, level, bo_usage,
SI_RESOURCE_FLAG_FORCE_LINEAR);
bo_flags);
/* Since depth-stencil textures don't support linear tiling,
* blit from ZS to color and vice versa. u_blitter will do